| Age | Commit message (Expand) | Author |
|---|
| 2015-07-22 | Fixed verilog so it emits non-random inital values. Changed Not to be | Adam Izraelevitz |
| 2015-07-21 | Firrtl generates verilog that compiles, but does not work | Adam Izraelevitz |
| 2015-07-21 | Fixed bug in fix :P | azidar |
| 2015-07-21 | Fixed removing non-referenced components | azidar |
| 2015-07-21 | Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl | azidar |
| 2015-07-21 | Updated TODO | azidar |
| 2015-07-21 | Made things go faster. Still in progress. Expand when now removes | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-16 | Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtl | azidar |
| 2015-07-16 | Fixed rename to work with chisel3 stuff | azidar |
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Updated flo backend | azidar |
| 2015-07-14 | Passes riscv-mini tests | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Added chisel feedback to firrtl spec. Datapath_new triggers too large a width... | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | Partial commit | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-14 | Fixed bug in lowering, where the indexes to many-connects and accessors weren... | azidar |
| 2015-07-13 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-10 | Added clock support | azidar |
| 2015-07-07 | Updated flo backend | azidar |
| 2015-07-07 | Passes riscv-mini tests | azidar |
| 2015-07-07 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-06 | Added chisel feedback to firrtl spec. Datapath_new triggers too large a width... | azidar |
| 2015-07-06 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-06 | Partial commit | azidar |
| 2015-07-06 | In progress commit | azidar |
| 2015-07-06 | Updated todo | azidar |
| 2015-07-02 | Added firrtl-lexer | azidar |
| 2015-07-02 | Fixed performance bugs, runs 7x faster | azidar |
| 2015-07-02 | Fixed stanza, optimize works, added a time printout | azidar |
| 2015-07-02 | Hopefully fixed stanza so it can correctly compile itself | azidar |
| 2015-07-01 | Updated TODO. | azidar |
| 2015-06-30 | Updated TODO. Ran spelling/grammar check on spec | azidar |
| 2015-06-29 | Fixed minor typos. As of now, the finished version for internal feedback. | azidar |
| 2015-06-26 | Changed clock from port kind to type | azidar |
| 2015-06-26 | Finished draft of Version 0.1.3. Ready for comments. | azidar |
| 2015-06-23 | More updates to spec | azidar |
| 2015-06-22 | Updated spec to remove Register,WritePort,ReadPort,RdWrPort,biaccessors | azidar |
| 2015-06-12 | Added more changes to spec | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-05 | Added updated stanza | azidar |
| 2015-06-05 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-06-05 | Added most recent pdf | azidar |
| 2015-06-05 | Commited most recent pdf | azidar |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to gene... | azidar |
| 2015-06-04 | Added Adam's changes to stanza | azidar |
