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2020-11-16bump antlr4 (#1936)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-16make LazyLogging log to console by default. (#1961)Jiuyang Liu
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-16Switch to allowlist in Travis SNAPSHOT publishing (#1962)Jack Koenig
2020-11-12Automatically publish SNAPSHOTs on pushes to master (#1955)Jack Koenig
Uses sbt-ci-release for automation
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
It would replace them with a validif node with a UIntLiteral which can lead to type errors.
2020-11-11smt: add support for write-first memories (#1948)Kevin Laeufer
2020-11-10Bump SNAPSHOT version (#1947)Jack Koenig
2020-11-10Fix SMT Memory Bug (#1942)Kevin Laeufer
* smt: add test for write port collision * smt: add missing call to insertDummyAssignsForMemoryOutputs * smt: fix typo in write port code Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-10Refactor emiter (#1879)Jiuyang Liu
* split big Emitter to submodules. * fix all deprecated warning. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-09smt: ensure that all signals have a unique name (#1943)Kevin Laeufer
* smt: add tests for assert name clashes * smt: ensure unique signal names with a namespace this fixes issues #1934
2020-11-07-full64 is required to detect VCS. (#1930)Jiuyang Liu
2020-11-04Remove caching from RenameMap (#1938)Jack Koenig
2020-11-04Add 1.4.x to Mergify (#1920)Jack Koenig
2020-10-27Merge pull request #1932 from freechipsproject/fix_VerilogPrepJiuyang Liu
Fix verilog prep
2020-10-26fix for LoweringCompilersSpec.Jiuyang liu
2020-10-26bug fix for VerilogPrep using wrong type.Jiuyang liu
2020-10-26fix a test not detecting verilog name conflicts.Jiuyang liu
2020-10-13Make {Stage, FirrtlStage}.run protected (#1926)Schuyler Eldridge
* Make Stage.run protected Change the access modifier of Stage.run from no modifier to protected. This method is really an internal API that the user implements with the main entry point for a Stage being "execute" or "transform". By allowing users to access "run" they can bypass checks, mandatory file reads/writes, and wrappers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Make FirrtlStage.run protected Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2020-10-12Update junit to 4.13.1 (#1925)Scala Steward
2020-10-05Merge pull request #1915 from freechipsproject/fix-negative-literal-fixupJack Koenig
Fix "fix" for negative literals > 32 bits
2020-10-01Fix "fix" for negative literals > 32 bitsJack Koenig
Overflow of 32-bit Int would cause any negative literal value equal to -(2^(width % 32 - 1)) where width >= 32 to be incorrectly inverted
2020-09-30Merge pull request #1908 from freechipsproject/fix-direct-mem-to-mem-connsAlbert Magyar
VerilogMemDelays: fix lowering of direct mem-to-mem connections
2020-09-30Add test for chaining RW-port rdata as wdata of another memAlbert Magyar
* Also clean up VerilogMemDelaySpec structure
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-30Speed up writing CustomFileEmission with buffering (#1906)Jack Koenig
Also speed up common case of Array[Byte]
2020-09-28License reference in maven publishing info (#1907)Chick Markley
now points to apache 2.0
2020-09-23Improve Travis Chisel tests (#1903)Jack Koenig
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-09-15Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)Jack Koenig
Both use EliminateTargetPaths to duplicate modules based on annotations. Currently, EliminateTargetPaths API is a little too limited so it duplicates more than it should which effectively breaks Dedup whenever DontTouchAnnotations are present. Also, make ConstProp and DCE treat all HasDontTouches as local annotations even if they are instance annotations. This is more conservative but it is generally better to preserve deduplication than to maximally optimize every instance. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-14Hit connect case in DedupModuleTests (#1716)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-10Merge pull request #1892 from freechipsproject/chisel-test-branchesAlbert Magyar
Specify appropriate Chisel and Treadle branches for CI tests
2020-09-10Specify appropriate Chisel and Treadle branches for CI testsAlbert Magyar
2020-09-09Make StageOption Unserializable (#1891)Jack Koenig
These options are generally specific to a stage and thus should not be propagating across serialization
2020-09-09Loosen inlining restrictions (#1882)Albert Chen
* test multiinfo comparison and mux cond inlining * loosen inlining conditions * fix typo * include dshlw * fix test
2020-09-06Add --pretty:no-expr-inlining to prevent expression inlining (#1869)Jack Koenig
Also rename --Wno-scala-version-warning to --warn:no-scala-version-deprecation and adopt naming convention where resulting annotation matches the CLI option
2020-09-06Support binary files in CustomFileEmission (#1887)Jack Koenig
2020-09-05Better error messages for unserializable annotations (#1885)Jack Koenig
2020-09-04Merge pull request #1883 from freechipsproject/legalize-mem-clocksAlbert Magyar
Legalize mem port clocks to avoid Verilator-unfriendly sensitivity lists
2020-09-04Add test for mem port clock legalizationAlbert Magyar
2020-09-04Legalize memory port clocksAlbert Magyar
2020-09-01InlineBooleanExpressions: test DontTouch (#1880)Albert Chen
* InlineBooleanExpressions: test DontTouch * run scalafmt
2020-09-01Merge pull request #1877 from freechipsproject/mill_patchJiuyang Liu
Make mill compatiable to 2.13.
2020-09-01reuse CrossSbtModule, make mill compatiable to 2.13.Jiuyang liu
2020-08-31Emitter: add missing parenthesize calls (#1874)Albert Chen
2020-08-28Merge pull request #1875 from freechipsproject/fix-inline-boolsAlbert Magyar
Restrict boolean inlining to avoid context-sensitive width bugs
2020-08-28Add test for InlineBooleanExpressions add-not exampleAlbert Magyar
2020-08-28Restrict boolean inlining to avoid context-sensitive width bugsAlbert Magyar
* Restore depth-agnostic inlining for simple 'lhs = ref' bool assignments * Address review comments * Run scalafmt
2020-08-28Merge pull request #1876 from freechipsproject/equiv-test-transform-orderAlbert Magyar
Add custom transforms 'upstream' of emitter annotation in equiv tests
2020-08-28Add custom transforms 'upstream' of emitter annotation in equiv testsAlbert Magyar
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
* FlattenSpec: flattening a module with no instaces should be a no-op * Fix problem when flattening/inlining a lone module Fix an edge case bug in InlineInstances where a circuit containing a lone module is flattened/inlined. This now properly special cases the situation of an empty indexMap which before had to be of length >= 1. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Simplify rename logic in InlineInstances Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Mea culpa Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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