| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-01-17 | Add firrtl-mode to README.md (#730) | Schuyler Eldridge | |
| Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> | |||
| 2018-01-15 | WiringTransform Refactor (#648) | Schuyler Eldridge | |
| Massive refactoring to WiringTransform with the use of a new EulerTour class to speed things up via fast least common ancestor (LCA) queries. Changes include (but are not limited to): * Use lowest common ancestor when wiring * Add EulerTour class with naive and Berkman-Vishkin RMQ * Adds LCA method for Instance Graph * Enables "Two Sources" using "Top" wiring test as this is now valid * Remove TopAnnotation from WiringTransform * Represent WiringTransform sink as `Seq[Named]` * Remove WiringUtils.countInstances, fix imports * Support sources under sinks in WiringTransform * Enable internal module wiring * Support Wiring of Aggregates h/t @edcote fixes #728 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Reviewed-by: Jack Koenig<jack.koenig3@gmail.com> | |||
| 2018-01-09 | Update README.md | Adam Izraelevitz | |
| 2018-01-08 | Typo: ExecutionOptionManager -> ExecutionOptionsManager. | Leway Colin | |
| 2018-01-05 | Fix FirrtlExecutionOptions backward incompatible change (#704). (#720) | Jim Lawson | |
| Fix FirrtlExecutionOptions backward incompatible change (#704). New options should be added to the end of the list to reduce backward compatibility problems. Update comment to mention backwards compatibility issue. | |||
| 2018-01-05 | Remove erroneous undef of RANDOMIZE in emitted Verilog | Jack Koenig | |
| 2017-12-29 | Add support for multiple annotation files | Jack | |
| Change loadAnnotations to return annotations instead of mutating firrtlOptions Deprecate implicit annotation file (top.anno) and annotation file override | |||
| 2017-12-29 | Actually emit annotations as YAML instead of default toString | Jack | |
| 2017-12-29 | Remove option --force-append-anno-file, make default | Jack Koenig | |
| The logic around this option was unintuitive and led to silently dropped annotations. | |||
| 2017-12-29 | Add Driver.dramaticWarning | Jack | |
| 2017-12-29 | Add logger printing for declarations removed by DCE | Jack Koenig | |
| 2017-12-29 | Add NodeCount analysis for helping with performance debugging | Jack Koenig | |
| 2017-12-27 | Removed top preamble (#640) | Adam Izraelevitz | |
| 2017-12-26 | Adjust isVCSAvailable comment | edwardcwang | |
| 2017-12-26 | Update ISSUE_TEMPLATE.md | Adam Izraelevitz | |
| Updated wording | |||
| 2017-12-26 | Update ISSUE_TEMPLATE.md | Adam Izraelevitz | |
| 2017-12-24 | Spec erroneously says mod instead of rem. | Paul Rigge | |
| 2017-12-22 | API change: out-of-bounds vec accesses now invalid, not first element (#685) | Adam Izraelevitz | |
| [skip formal checks] Generate nicer name for remove accesses | |||
| 2017-12-20 | Verify shl/shr amount is > 0 (#710) | Jim Lawson | |
| Fixes #527 | |||
| 2017-12-20 | Fix bug in ConstProp where module dependency edges were dropped (#696) | Jack Koenig | |
| This resulted in parent modules sometimes being constant proppagated before a child module. If the child module has a constant driving one of its outputs, the parent module would thus not see the constant. This resulted in strange unstable constant propagation behavior where sometimes constant outputs would not propagate. Also add test illustrating why this occurs with uses of InstanceGraph | |||
| 2017-12-20 | Make submodule inputs void in ExpandWhens (#706) | Jack Koenig | |
| 2017-12-20 | Add "checker" to the set of Verilog keywords - fixes 455. (#711) | Jim Lawson | |
| 2017-12-19 | support -X sverilog to output xxxx.sv file (#638) | Wei Song (宋威) | |
| 2017-12-19 | Make toNamed invert serialize (#709) | Schuyler Eldridge | |
| Fixes #708 | |||
| 2017-12-18 | Create ISSUE_TEMPLATE.md (#699) | Adam Izraelevitz | |
| 2017-12-18 | Bump sbt (#703) | Jack Koenig | |
| Bump SBT to 1.0.4 and update plugins Update Scala versions and sbt commands in .travis.yml Replace run-main with runMain | |||
| 2017-12-15 | getBuildDir now builds full path | Adam Izraelevitz | |
| 2017-12-12 | Merge pull request #684 from freechipsproject/remove-wires | Jack Koenig | |
| Remove wires, replacing them with nodes | |||
| 2017-12-12 | Refactor formal equivalence CI test | Jack Koenig | |
| Make the check script allow different designs Add FPU, ICache, and RocketCore to regress and use instead of Rob for CI equivalence check | |||
| 2017-12-12 | Add RemoveWires transform | Jack Koenig | |
| This transform replaces all wires with nodes in a legal, flow-forward order | |||
| 2017-12-12 | Improve MultiInfo emission, add apply that squashes NoInfo | Jack Koenig | |
| 2017-12-12 | Make object ConstantPropagation utils | Jack Koenig | |
| Move pad to object ConstantPropagation so other transforms can use it | |||
| 2017-12-12 | Bump scala and plugins. (#694) | Jim Lawson | |
| 2017-11-29 | Add alternative graph IR (#671) | Wenyu Tang | |
| * add graph node classes * add graph representation usage pass * remove pass using graph nodes so that firrtl can compile * move google graph ir nodes to altIR package | |||
| 2017-11-28 | Have DedupModules report renaming | Jack | |
| 2017-11-28 | Refactor RenameMap to rename Components if their Module is renamed | Jack | |
| 2017-11-16 | Move digraph exceptions out of digraph class (#688) | Albert Magyar | |
| 2017-11-16 | Make Yosys equivalence check more robust (#686) | Jack Koenig | |
| Also let Travis know that equivalence checks can take a while | |||
| 2017-11-10 | Make digraph methods deterministic (#653) | Albert Magyar | |
| 2017-11-08 | Add InfoSpec for checking Info propagation | Jack Koenig | |
| 2017-11-08 | Add FirrtlCheckers and scalatest helpers for testing | Jack Koenig | |
| 2017-11-08 | Emit source locators as comments in emitted Verilog | Jack Koenig | |
| 2017-10-31 | Fix bug emitting and reparsing ExtModule String parameters (#675) | Jack Koenig | |
| 2017-10-03 | Merge pull request #670 from freechipsproject/add-formal-check | Jack Koenig | |
| Add Yosys formal equivalence checking to Travis regressions | |||
| 2017-10-01 | Add script for formally comparing emitted Verilog | Jack Koenig | |
| Also add Travis test for running this script on PRs | |||
| 2017-10-01 | Add Yosys 0.7 install | Jack Koenig | |
| 2017-10-01 | Remove redundant tests from Travis | Jack | |
| 2017-09-30 | Make ReplaceAccesses optimize multi-dimensional accesses (#665) | Albert Magyar | |
| 2017-09-30 | Update README.md to link tech report (#550) | Adam Izraelevitz | |
| 2017-09-30 | Fixed zero width cat but (#651) | Adam Izraelevitz | |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |