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2020-02-12Update commons-text to 1.8 (#1333)Scala Steward
2020-02-11Update junit to 4.13 (#1332)Scala Steward
2020-02-11Update protoc-jar to 3.11.1 (#1330)Scala Steward
2020-02-11Update sbt-unidoc to 0.4.2 (#1329)Scala Steward
2020-02-11Update sbt-buildinfo to 0.9.0 (#1328)Scala Steward
2020-02-11Update sbt-assembly to 0.14.10 (#1327)Scala Steward
2020-02-11Update sbt-scalafix to 0.9.11 (#1326)Scala Steward
2020-02-11[spec] Change sub(UInt, UInt) output type to UInt (#1378)Albert Magyar
2020-02-10Merge pull request #1370 from freechipsproject/issue-1309Schuyler Eldridge
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
2020-02-10Rename modules when duplicating instancesSchuyler Eldridge
2020-02-10Add Target utility referringModuleSchuyler Eldridge
2020-02-07Merge pull request #1366 from freechipsproject/dueling-const-propAlbert Magyar
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-07Refactor handling of reg const prop entries to cover more casesAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
2020-02-06Merge pull request #1362 from freechipsproject/andr-reduction-base-caseSchuyler Eldridge
2020-02-06Add note to spec about reductions on zero-width wiresAlbert Magyar
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-02-03Dedup: check if moduleOpt exists before getting (#1323)Albert Chen
2020-02-03Fix conversion of Reference-containing expressions to ReferenceTargets (#1349)Albert Magyar
2020-01-28add IsModule, IsMember, CompleteTarget serializers (#1321)Albert Chen
2020-01-21Refactoring checkCatArgumentLegality (#1317)Derek Pappas
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
2020-01-15improve the tail ir usability. (#1241)Sequencer
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
2020-01-10Change LoggerState.globalLevel to Warn (#1307)Jim Lawson
2020-01-10Change default LogLevel to Warn (#1305)Schuyler Eldridge
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
2020-01-07Merge pull request #1259 from freechipsproject/cleanup-testing-consoleJack Koenig
2020-01-07Change printing of FIRRTL runtime from error to warnJack Koenig
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
2020-01-07Merge pull request #1264 from freechipsproject/cleanup-verilog-emitter-castsJack Koenig
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-07Fix .run_formal_checks.sh skipping logic (#1297)Jack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
2019-12-31Merge pull request #1291 from freechipsproject/infer-resets-last-connect-sema...Jack Koenig
2019-12-30Minor code cleansup in InferResetsJack Koenig
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
2019-12-18Fix incorrect ScalaDoc link (#1282)Schuyler Eldridge
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