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[F764.1] Bump scopt from 3.6.0 -> 3.7.0
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This provides support for increased introspection of options inside of
scopt, e.g., getting an options short option (shortOpt).
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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(#883)
* Filter resource file names to avoid including the same file multiple times.
Addresses issue #882.
* Use a Set instead of a Map to filter Verilog files.
* Use canonical paths for file name comparison and unify name generation.
Provide a common method for copying resources to a directory to ensure the same resource ends up with the same name if it's copied by multiple clients.
* Reduce confusion - another absolute -> canonical switch.
Use the canonical path on the verilator command line for the filter additional Verilog sources.
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Previously, mems marked no dedup would prevent mems with the same
instance name in other modules from deduping
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[764: opts/annos] Easy conversion of String => LogLevel.value
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This adds an apply method to the LogLevel object for conversion from a
String to a LogLevel.value.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Allow the #delay before random initialization to be overridden
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The default of 0.002 can be less than the Verilog time precision, which
effectively causes it to be rounded down to 0. So, allow the user to
`define RANDOMIZE_DELAY to some other value.
If the macro is not defined, the old behavior is preserved.
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* Bump to Scala 2.12.6 and make it the default.
* Use Scala 2.11.12 for chisel tests.
* Try with Scala 2.12.4.
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- Fixed edge case file name that starts with . and has no suffix
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Fixes #780
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- makes RemoveWires properly include registers in dependency graph
- adds an apply method to WRef for DefNode
- adds a test case requiring register reordering
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Fixes a bug where registers could be instantiated after nodes that
referred to them
Also add WRef.apply utility for nodes
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* Support for load memory annotations in chisel
This PR
* Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
* remove from VerilogCompiler
* move to VerilogEmitter
* Changes the verilog emitter to allow programmatic access to the verilog module declaration
* Creating a bindable module requires headers to match
* Provides a unit test that shows how to generate a bindable module.
* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading
* Binding support
- Fixed bug that handled suffixes on memory initializing files
* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer
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* add FoldADD to const prop, add yosys miter tests
* add option for verilog compiler without optimizations
* rename FoldLogicalOp to FoldCommutativeOp
* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation
* add constant propagation for Tail DoPrims
* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim
* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
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Previously, Vecs of Bundles that contained a zero-width element would
result in a ClassCastException
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On circuits with large numbers of width inferences, prepend to a linked
list instead of appending and having to make a copy.
Fixes #842
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This caused wrong message: "File a Firrtl Issue"
Instead of the correct "Reference XX is not fully initialized"
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[skip formal checks] LEC passes with Formality
* Improve code generation for smem RW-port wmode port
A common case for these port-enables is
wen = valid & write
ren = valid & !write
which the RW-port transform currently turns into
en = (valid & write) | (valid & !write)
wmode = valid & write
because it proved `wen` and `ren` are mutually exclusive via `write`.
Synthesis tools can trivially optimize `en` to `valid`, so that's not a
problem, but the wmode field can't be optimized if going into a black box.
This PR instead sets `wmode` to whatever node was used to prove
mutual exclusion, which is always a simpler expression. In this case:
en = (valid & write) | (valid & !write)
wmode = write
* In RemoveCHIRRTL, infer mask relative to port definition
Previously, it was inferred relative to the memory definition causing
the mask condition to be redundantly conjoined with the enable signal.
Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to
improve QoR.
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Fixes #756
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Add support for ProtoBuf serialization and deserialization
* Add support for additional features in .proto description
Features added: Info, Fixed[Type|Literal], AnalogType, Attach, Params
* Add support for .pb input files
This involves an API change where FIRRTL no longer implicitly adds .fir
to input file names
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Match https://github.com/freechipsproject/chisel3/pull/783
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This fixes --infer-rw to not expect an argument. After the annotations
refactor, no option was required, but some legacy code remained.
This also updates the test cases to be more correct and not specify an
option to --infer-rw.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Update Parser to use ANTLR CharStreams
This removes some unnecessary object creation in String reading and
manipulation
* Remove two unnecessary traversals from Block construction in Visitor
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Relying on /tmp as a place for test output will fail on multiuser systems and may fail if multiple instances of tests are running for the same user.
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Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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It does not provide anything over NoTargetAnnotation. Its existence
suggests some significance so removing it for clarity.
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Escape raw params using \'
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Also minor cleanup to literal construction in Visitor
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Useful if you want to find out how a node was reachable and you used a blacklist during the reachability analysis
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Add optional argument to verilogToCpp to suppress VCD
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This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator
Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
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Makes ExpandWhens preserve connect Infos
Also fix Travis regressions
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* Switch Yosys back to 0.7 with patch for moved ABC repo
* Add 30 min timeout for LEC tests
* h/t https://stackoverflow.com/questions/43918874#44007537
* Move Travis building of Verilator and Yosys to prelude stage
* Don't use automatic Travis Scala tests, do it manually
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* Collects Infos found for symbols
* Merges multiple sources for symbol into MultiInfo
* Restores these Infos on connect statements.
* Add test showing preserved Infos
* Changed ++ methods on the Info sub-classes
* Ignore NoInfo being added
* Fixed way adding was implemented in MultiInfo
* Made InfoMap a class which defines the default value function
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* Make VerilogEmitter properly handle pad of width <= width of arg
* Constant prop pads with pad amount <= width of arg
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