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2018-10-30Fix $TRAVIS_COMMIT_RANGE (#927)Schuyler Eldridge
2018-10-28Fix TRAVIS_COMMIT_RANGE in .run_chisel_tests, replace ... with .. (#924)Jack Koenig
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
2018-10-24Instance Annotations (#865)Adam Izraelevitz
2018-10-24Merge pull request #921 from seldridge/f893Schuyler Eldridge
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
2018-10-16Added reference to ICCAD paper (#915)Adam Izraelevitz
2018-10-12Merge pull request #909 from seldridge/issue-729.2Schuyler Eldridge
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
2018-10-12Verilog renaming uses "_", works on whole ASTSchuyler Eldridge
2018-10-05Merge pull request #901 from seldridge/issue-729.1Schuyler Eldridge
2018-10-03Inlining uses "_", respects namespacesSchuyler Eldridge
2018-10-03Make some Uniquify methods private [firrtl]Schuyler Eldridge
2018-10-03Add cloneUnderlying method to NamespaceSchuyler Eldridge
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-27Number all code examples & add specification build to Makefile (#894)Ben Marshall
2018-09-27Add Utils.expandPrefixes as Prefix Unique helper (#900)Schuyler Eldridge
2018-09-26Merge pull request #898 from seldridge/port-uniqueness-checksSchuyler Eldridge
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
2018-09-21Add CODEOWNERS file (#895)Albert Magyar
2018-09-13Do not remove ExtMods with no ports by default (#888)albertchen-sifive
2018-09-07Bug Fixes in TopWiring (#885)alonamid
2018-08-30Emit Verilog Comments (#874)albertchen-sifive
2018-08-29Merge pull request #878 from seldridge/issue-764-refactor-pr-pointer-systemVe...Schuyler Eldridge
2018-08-29Add SystemVerilogCompiler classSchuyler Eldridge
2018-08-29Merge pull request #875 from seldridge/issue-764-refactor-pr-pointerSchuyler Eldridge
2018-08-29Bump scopt from 3.6.0 -> 3.7.0Schuyler Eldridge
2018-08-29Filter resource file names to avoid including the same file multiple times. (...Jim Lawson
2018-08-24Update DontTouchAnnotation not found error message (#864)Jack Koenig
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
2018-08-23Merge pull request #877 from seldridge/issue-764-refactor-pr-pointer-loglevelSchuyler Eldridge
2018-08-23Add LogLevel apply for String => LogLevel.ValueSchuyler Eldridge
2018-08-21Merge pull request #872 from freechipsproject/randomize-delayAndrew Waterman
2018-08-21Allow the #delay before random initialization to be overriddenAndrew Waterman
2018-08-21Make Scala 2.12.4 the default. (#848)Jim Lawson
2018-08-17Binding support (#854)Chick Markley
2018-08-14Add targetDirName test (#869)Leway Colin
2018-08-10allowing overrides to $random (#859)Deborah Soung
2018-08-08Use LinkedHashSet in propagateAnnotations (#855)albertchen-sifive
2018-08-07Respect register references in RemoveWires (#868)Schuyler Eldridge
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
2018-08-03add link to repo for firrtl syntax highlighting in sublime text 3kritik bhimani
2018-08-03Fix Travis (#858)Jack Koenig
2018-07-26Support for load memory annotations in chisel (#833)Chick Markley
2018-07-20Constant prop add (#849)albertchen-sifive
2018-07-11Make InstanceGraph have deterministic and use defined iteration order (#843)Jack Koenig
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-07-10InferWidths: improve performance (#846)edwardcwang
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