| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-06 | Added starter code for SMem replacement | Angie | |
| 2016-09-05 | Change null statement to empty begin end (#264) | Colin Schmidt | |
| this eliminates warnings in recent versions of VCS | |||
| 2016-08-31 | Bump version number in preparation for release. | Jim Lawson | |
| 2016-08-25 | emit wires instead of registers for invalid randomization | Howard Mao | |
| Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires. | |||
| 2016-08-25 | update verilog generation test | Howard Mao | |
| 2016-08-25 | Finer grained control over randomization | Howard Mao | |
| We previously had `ifdef guards on some parts of the emitted verilog to control whether some registers or nets should be given random initial values. These guards were all dependent on the RANDOMIZE macro. However, there were actually three separate cases being controlled 1. Giving random values to disconnected wires 2. Random initialization of registers 3. Random initialization of memories It is possible that the designer would want to switch these three on or off independently in simulation. For instance, the latter two are usually safe because registers and memories will get some definite binary value at power on in the actual circuit, but the first one can be quite dangerous because the undriven wire could be metastable. This change provides separate macros for each of the three sets of guards so that they can be controlled independently. | |||
| 2016-08-18 | emit correct enable signals for memories (#242) | Donggyu | |
| 2016-08-18 | Add MemUtils to aid in interfacing with alternate memory implementations (#244) | Albert Magyar | |
| 2016-08-18 | Remove redundant test and errors.append() in check_types_e(). (#243) | Jim Lawson | |
| 2016-08-17 | Change RW port names (#236) | Angie Wang | |
| * Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch. | |||
| 2016-08-17 | Fixed cmdline usage string (#235) | Adam Izraelevitz | |
| Now prints usage when given incorrect arguments | |||
| 2016-08-16 | Spec bugfix: update concrete reg syntax example (#233) | Adam Izraelevitz | |
| Also added clock to reg's abstract syntax | |||
| 2016-08-16 | add test case for clock type connection (#239) | mwachs5 | |
| 2016-08-15 | Update README.md | Adam Izraelevitz | |
| Added help string #234 | |||
| 2016-08-15 | Update README.md | Adam Izraelevitz | |
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz | |
| * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) | |||
| 2016-08-12 | Fix calculation of runtime for ANTLR Parser (#229) | Jack Koenig | |
| 2016-08-12 | Merge pull request #228 from mwachs5/connect_clock_type | Adam Izraelevitz | |
| Add missing case for connecting ClockType | |||
| 2016-08-12 | Add missing case for connecting ClockType | Megan Wachs | |
| 2016-08-09 | provide parser for naive string (#227) | Donggyu | |
| 2016-08-09 | Merge pull request #226 from ucb-bar/fix_mem_enables | Chick Markley | |
| fix read port enables in RemoveCHIRRTL LGTM -chick | |||
| 2016-08-09 | fix read port enables in RemoveCHIRRTL | Donggyu Kim | |
| read port enables for cmems should always be high | |||
| 2016-08-08 | Merge pull request #223 from ucb-bar/dont-create-files-on-failure | Adam Izraelevitz | |
| Don't create output files until the compiler succeeds | |||
| 2016-08-08 | Don't create output files until the compiler succeeds | Andrew Waterman | |
| Creating the output file preemptively screws up make, as on subsequent executions of make, it thinks the task succeeded. | |||
| 2016-08-05 | Merge pull request #220 from ucb-bar/fix-width-error-msg | Adam Izraelevitz | |
| Bugfix: recursing stmts to remove unknown widths | |||
| 2016-08-04 | Added RemoveEmpty.scala, which removes Empty and nested Blocks (#218) | Adam Izraelevitz | |
| * Added RemoveEmpty.scala, which removes Empty and nested Blocks * Reused squashEmpty from ExpandWhens by moving it to Utils * Squash EmptyStmts in ExpandWhens correctly | |||
| 2016-08-04 | Addd check: bits, tail, head arg width | azidar | |
| 2016-08-04 | Bugfix: recursing stmts to remove unknown widths | azidar | |
| 2016-08-03 | fixes small mistakes in serialize (#216) | Donggyu | |
| 2016-08-02 | Merge pull request #215 from ucb-bar/new-serialize | Adam Izraelevitz | |
| Change serialize to abstract method on FirrtlNode | |||
| 2016-08-02 | Merge pull request #203 from ucb-bar/fix_mem_infer | Adam Izraelevitz | |
| Fix mem infer | |||
| 2016-08-02 | make infer readwrite ports optional | Donggyu Kim | |
| turned on with '--inferRW <circuit name>' | |||
| 2016-08-02 | Change serialize to abstract method on FirrtlNode | Jack Koenig | |
| 2016-08-02 | Merge pull request #214 from ucb-bar/fix-thread-unsafety | Adam Izraelevitz | |
| Fix use of global state in instance loop checking | |||
| 2016-08-02 | Merge pull request #213 from ucb-bar/default-to-warn | Adam Izraelevitz | |
| Change default log level to warn | |||
| 2016-08-02 | Merge pull request #211 from ucb-bar/fix-subaccess | Adam Izraelevitz | |
| Refactor RemoveAccesses and fix bug #210. | |||
| 2016-08-02 | Fix use of global state in instance loop checking | jackkoenig | |
| Also increase sensitivity of thread safety checking Fixes #159 | |||
| 2016-08-01 | Merge pull request #208 from ucb-bar/no_constprop | Adam Izraelevitz | |
| remove ConstProp in HighFirrtlToMiddleFirrtl | |||
| 2016-08-01 | Merge pull request #212 from ucb-bar/fix-validChar | Adam Izraelevitz | |
| Fix StringSpec generators to only choose from valid values. | |||
| 2016-08-01 | Added minor cosmetic changes to RemoveAccesses | azidar | |
| 2016-08-01 | Change default log level to warn | Jack Koenig | |
| 2016-08-01 | Refactor RemoveAccesses and fix bug #210. | azidar | |
| Added corresponding unit test. | |||
| 2016-08-01 | Fix StringSpec generators to only choose from valid values. | Jack Koenig | |
| The old almost equivalent syntax gives the same result but can cause the test to fail if too many invalid values are thrown away. | |||
| 2016-07-29 | remove ConstProp in HighFirrtlToMiddleFirrtl | Donggyu Kim | |
| ConstProp before width padding causes errors for SIntLiteral | |||
| 2016-07-28 | Merge pull request #207 from ucb-bar/fix-width-bug | Donggyu | |
| InferWidths now only fixes declaration widths | |||
| 2016-07-28 | InferWidths now only fixes declaration widths | azidar | |
| Then calls InferTypes to propagate inferred widths to expressions. Required upgrading InferTypes to do simple width propagation. Fixes #206 and #200. | |||
| 2016-07-27 | infer readwrite ports for backward compatibility | Donggyu Kim | |
| 2016-07-27 | fix read port enables in RemoveCHIRRTL | Donggyu Kim | |
| read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced | |||
| 2016-07-27 | Merge pull request #205 from ucb-bar/add-future-release | Adam Izraelevitz | |
| Added future-release.txt | |||
| 2016-07-27 | Merge pull request #199 from ucb-bar/add-annotations | Adam Izraelevitz | |
| Rework Annotations | |||
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |