diff options
Diffstat (limited to 'test')
34 files changed, 398 insertions, 193 deletions
diff --git a/test/chirrtl/infer-mport-dir.fir b/test/chirrtl/infer-mport-dir.fir new file mode 100644 index 00000000..50baeff2 --- /dev/null +++ b/test/chirrtl/infer-mport-dir.fir @@ -0,0 +1,22 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; CHECK: Done! +circuit top : + module top : + input clk : Clock + wire p : UInt + wire q : UInt + cmem m : {a:UInt<4>,b:UInt<4>}[10] + p <= UInt(1) + q <= UInt(1) + wire x : {a:UInt<4>,b:UInt<4>} + x.a <= UInt(1) + x.b <= UInt(1) + when p : + infer mport a = m[UInt(3)],clk + infer mport b = m[UInt(3)],clk + infer mport c = m[UInt(3)],clk + when q : + a <= x + x <= b + c <= x + x <= c diff --git a/test/chirrtl/mask-bug.fir b/test/chirrtl/mask-bug.fir new file mode 100644 index 00000000..b580c075 --- /dev/null +++ b/test/chirrtl/mask-bug.fir @@ -0,0 +1,20 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; CHECK: Done! +circuit top : + module top : + input clk : Clock + wire p : UInt + wire q : UInt + cmem m : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}[10] + p <= UInt(1) + q <= UInt(1) + wire x : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}} + x.a <= UInt(1) + x.b.c <= UInt(1) + x.b.d <= UInt(1) + when p : + write mport a = m[UInt(3)],clk + when q : + a <- x + + diff --git a/test/chirrtl/wacc-wdc.fir b/test/chirrtl/wacc-wdc.fir index 32b61c3b..779722da 100644 --- a/test/chirrtl/wacc-wdc.fir +++ b/test/chirrtl/wacc-wdc.fir @@ -3,35 +3,54 @@ circuit top : module top : input clk : Clock wire p : UInt - cmem m : UInt<4>[10] + wire q : UInt + cmem m : {a:UInt<4>,b:UInt<4>}[10] p <= UInt(1) + q <= UInt(1) + wire x : {a:UInt<4>,b:UInt<4>} + x.a <= UInt(1) + x.b <= UInt(1) when p : - write mport a = m[UInt(3)],clk,UInt(1) - a <= UInt(2) + write mport a = m[UInt(3)],clk + when q : + a <= x -; CHECK: To FIRRTL -; CHECK: mem m : -; CHECK: data-type: UInt<4> -; CHECK: depth: 10 -; CHECK: write-latency: 1 -; CHECK: read-latency: 0 -; CHECK: writer: a -; CHECK: poison GEN : UInt<4> -; CHECK: poison GEN_1 : UInt<4> -; CHECK: m.a.addr <= GEN -; CHECK: m.a.clk <= clk -; CHECK: m.a.en <= UInt("h0") -; CHECK: m.a.data <= GEN_1 -; CHECK: m.a.mask <= UInt("h0") -; CHECK: p <= UInt("h1") -; CHECK: when p : -; CHECK: m.a.addr <= UInt("h3") -; CHECK: m.a.en <= UInt("h1") -; CHECK: m.a.mask <= UInt("h1") -; CHECK: m.a.data <= UInt("h2") +; CHECK: Remove CHIRRTL -; CHECK: Finished To FIRRTL +; CHECK: circuit top : +; CHECK: module top : +; CHECK: input clk : Clock +; CHECK: wire p : UInt +; CHECK: wire q : UInt +; CHECK: mem m : +; CHECK: data-type: { a : UInt<4>, b : UInt<4>} +; CHECK: depth: 10 +; CHECK: write-latency: 1 +; CHECK: read-latency: 0 +; CHECK: writer: a +; CHECK: poison GEN_0 : UInt<4> +; CHECK: poison GEN_1 : { a : UInt<4>, b : UInt<4>} +; CHECK: m.a.addr <= GEN_0 +; CHECK: m.a.clk <= clk +; CHECK: m.a.en <= UInt("h0") +; CHECK: m.a.data <= GEN_1 +; CHECK: m.a.mask.a <= UInt("h0") +; CHECK: m.a.mask.b <= UInt("h0") +; CHECK: p <= UInt("h1") +; CHECK: q <= UInt("h1") +; CHECK: wire x : { a : UInt<4>, b : UInt<4>} +; CHECK: x.a <= UInt("h1") +; CHECK: x.b <= UInt("h1") +; CHECK: when p : +; CHECK: m.a.addr <= UInt("h3") +; CHECK: m.a.en <= UInt("h1") +; CHECK: when q : +; CHECK: m.a.data <= x +; CHECK: m.a.mask.a <= UInt("h1") +; CHECK: m.a.mask.b <= UInt("h1") + +; CHECK: Finished Remove CHIRRTL ; CHECK: Done! diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir index 6c083905..7db78509 100644 --- a/test/errors/high-form/NumArgs.fir +++ b/test/errors/high-form/NumArgs.fir @@ -1,11 +1,9 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Primop mux requires 3 expression arguments. ; CHECK: Primop add requires 2 expression arguments. ; CHECK: Primop bits requires 2 integer arguments. circuit Top : module Top : - node x = mux(UInt(1),UInt(1)) node y = add(SInt(1),UInt(1),UInt(1)) node z = bits(UInt(1),1,2,3) diff --git a/test/errors/high-form/Prefix.fir b/test/errors/high-form/Prefix.fir index ed5245b3..ba4a28a2 100644 --- a/test/errors/high-form/Prefix.fir +++ b/test/errors/high-form/Prefix.fir @@ -1,10 +1,9 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Reference x$y and x share a prefix. -; XFAIL: * +; CHECK: Symbol x$z$y is a prefix. circuit Top : module Top : - wire x : UInt<1> - wire x$y : UInt<2> + wire x : UInt<2> + wire x$z$y : UInt<1> diff --git a/test/errors/type/AccessIndexUInt.fir b/test/errors/type/AccessIndexUInt.fir new file mode 100644 index 00000000..d47bb7c6 --- /dev/null +++ b/test/errors/type/AccessIndexUInt.fir @@ -0,0 +1,8 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: AccessIndexUInt.fir@8.4: [module Top] Access index must be a UInt type. +circuit Top : + module Top : + input b : UInt<32>[62] + input a : SInt<8> + output c : UInt<32> + c <= b[a] diff --git a/test/errors/type/MuxWithFlips.fir b/test/errors/type/MuxWithFlips.fir new file mode 100644 index 00000000..9a8b2170 --- /dev/null +++ b/test/errors/type/MuxWithFlips.fir @@ -0,0 +1,12 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; CHECK: [module Top] Must mux between passive types. +; CHECK: [module Top] A mux condition must be of type UInt. + +circuit Top : + module Top : + input c : SInt<1> + input x : {x : UInt, flip y : UInt} + input y : {x : UInt, flip y : UInt} + output z : {x : UInt, flip y : UInt} + z <= mux(c,x,y) + diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir index 0b8b9e6b..2030955f 100644 --- a/test/errors/type/NodeWithFlips.fir +++ b/test/errors/type/NodeWithFlips.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Node must be a ground type. +; CHECK: Node must be a passive type. circuit Top : module Top : diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir index f687c754..dcf19935 100644 --- a/test/errors/type/Primop.fir +++ b/test/errors/type/Primop.fir @@ -1,7 +1,7 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Primop mux requires all operands to have the same type. +; CHECK: Must mux between equivalent types. ; CHECK: Primop add cannot operate on non-ground types. -; CHECK: Primop mux requires argument SInt("h1") to be a UInt type. +; CHECK: A mux condition must be of type UInt. circuit Top : module Top : diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 5a81a62e..6261ec01 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s ;CHECK: Done! circuit Top : diff --git a/test/features/IsInvalid.fir b/test/features/IsInvalid.fir new file mode 100644 index 00000000..fbb69ef7 --- /dev/null +++ b/test/features/IsInvalid.fir @@ -0,0 +1,74 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +circuit Top : + module Top : + input clk : Clock + input reset : UInt<1> + input a : { w : UInt<42>, flip x : UInt<30>}[2] + output b : { w : UInt<42>, flip x : UInt<30>}[2] + mem m : + depth => 10 + data-type => UInt<32>[4] + read-latency => 0 + write-latency => 1 + reader => r + writer => w + read-writer => rw + wire x : { w : UInt<42>, x : UInt<20>} + reg c : { w : UInt<42>, x : UInt<20>},clk,reset,x + inst other of Other + + clk is invalid + reset is invalid + a is invalid + b is invalid + m is invalid + x is invalid + c is invalid + other is invalid + module Other : + input a : { w : UInt<42>, flip x : UInt<30>} + output b : { w : UInt<42>, flip x : UInt<30>} + b <= a + + +;CHECK: Expand Connects +;CHECK: skip +;CHECK: skip +;CHECK: a[0].x is invalid +;CHECK: a[1].x is invalid +;CHECK: b[0].w is invalid +;CHECK: b[1].w is invalid +;CHECK: m.r.addr is invalid +;CHECK: m.r.en is invalid +;CHECK: m.r.clk is invalid +;CHECK: m.w.data[0] is invalid +;CHECK: m.w.data[1] is invalid +;CHECK: m.w.data[2] is invalid +;CHECK: m.w.data[3] is invalid +;CHECK: m.w.mask[0] is invalid +;CHECK: m.w.mask[1] is invalid +;CHECK: m.w.mask[2] is invalid +;CHECK: m.w.mask[3] is invalid +;CHECK: m.w.addr is invalid +;CHECK: m.w.en is invalid +;CHECK: m.w.clk is invalid +;CHECK: m.rw.wdata[0] is invalid +;CHECK: m.rw.wdata[1] is invalid +;CHECK: m.rw.wdata[2] is invalid +;CHECK: m.rw.wdata[3] is invalid +;CHECK: m.rw.wmask[0] is invalid +;CHECK: m.rw.wmask[1] is invalid +;CHECK: m.rw.wmask[2] is invalid +;CHECK: m.rw.wmask[3] is invalid +;CHECK: m.rw.waddr is invalid +;CHECK: m.rw.wen is invalid +;CHECK: m.rw.raddr is invalid +;CHECK: m.rw.ren is invalid +;CHECK: m.rw.clk is invalid +;CHECK: x.w is invalid +;CHECK: x.x is invalid +;CHECK: c.w is invalid +;CHECK: c.x is invalid +;CHECK: other.a.w is invalid +;CHECK: other.b.x is invalid +;CHECK: Done! diff --git a/test/features/MemSize1.fir b/test/features/MemSize1.fir new file mode 100644 index 00000000..a29d3fc5 --- /dev/null +++ b/test/features/MemSize1.fir @@ -0,0 +1,11 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Done! +circuit Top : + module Top : + input clk : Clock + output out : UInt<32> + input i : UInt<1> + cmem m : UInt<32>[1] + read mport r = m[i],clk + out <= r + diff --git a/test/features/MuxBundle.fir b/test/features/MuxBundle.fir new file mode 100644 index 00000000..764078d5 --- /dev/null +++ b/test/features/MuxBundle.fir @@ -0,0 +1,16 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Expand Connects +circuit Top : + module Top : + input a: {w:UInt<42>,x:UInt<20>} + input b: {w:UInt<42>,x:UInt<20>} + input c: {w:UInt<42>,x:UInt<20>} + input p : UInt<1> + output d: {w:UInt<42>,x:UInt<20>} + d <= mux(p,mux(p,a,b),c) +;CHECK: d.w <= mux(p, mux(p, a.w, b.w), c.w) +;CHECK: d.x <= mux(p, mux(p, a.x, b.x), c.x) + +;CHECK: Finished Expand Connects +;CHECK: Done! + diff --git a/test/features/MuxNodeExamples.fir b/test/features/MuxNodeExamples.fir new file mode 100644 index 00000000..07fa16b4 --- /dev/null +++ b/test/features/MuxNodeExamples.fir @@ -0,0 +1,28 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Expand Connects +circuit Top : + module Top : + input a : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] + input b : {f:UInt<3>[3], flip g:UInt<3>[3]}[2] + input p : UInt<1> + input i : UInt<1> + b[0].g[0] <= UInt(0) + b[0].g[1] <= UInt(0) + b[0].g[2] <= UInt(0) + b[1].g[0] <= UInt(0) + b[1].g[1] <= UInt(0) + b[1].g[2] <= UInt(0) + a[0].g[0] <= UInt(0) + a[0].g[1] <= UInt(0) + a[0].g[2] <= UInt(0) + a[1].g[0] <= UInt(0) + a[1].g[1] <= UInt(0) + a[1].g[2] <= UInt(0) + node x = mux(p,a[i].f,b[i].f) + + + +;CHECK: Finished Expand Connects +;CHECK: Done! + + diff --git a/test/features/MuxType.fir b/test/features/MuxType.fir new file mode 100644 index 00000000..b0e7e7ef --- /dev/null +++ b/test/features/MuxType.fir @@ -0,0 +1,12 @@ + +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Expand Connects +circuit Top : + module Top : + input a: UInt<1> + input b: UInt<32> + input p : UInt<1> + output d: UInt + node y = mux(p, a, b) + d <= y +;CHECK:Done! diff --git a/test/features/NodeBundle.fir b/test/features/NodeBundle.fir new file mode 100644 index 00000000..c4c33107 --- /dev/null +++ b/test/features/NodeBundle.fir @@ -0,0 +1,12 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +;CHECK: Lower Types +circuit Top : + module Top : + input a: {w:UInt<42>,x:UInt<20>} + node d = a +;CHECK: node d_w = a_w +;CHECK: node d_x = a_x + +;CHECK: Finished Lower Types +;CHECK: Done! + diff --git a/test/features/ValidIf.fir b/test/features/ValidIf.fir new file mode 100644 index 00000000..70c69313 --- /dev/null +++ b/test/features/ValidIf.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +circuit Top : + module Top : + input clk : Clock + input reset : UInt<1> + input a : { w : UInt<42>, x : UInt<30>}[2] + input b : { w : UInt<42>, x : UInt<30>}[2] + input p: UInt<1> + input q: UInt<1> + output c : { w : UInt<42>, x : UInt<30>}[2] + output d : { w : UInt<42>, x : UInt<30>}[2] + + c is invalid + when p : + when q : + c <= a + else : + c <= b + d <= validif(p,b) + +;CHECK: Done! diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir new file mode 100644 index 00000000..f8fceaa9 --- /dev/null +++ b/test/features/VerilogRename.fir @@ -0,0 +1,18 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +circuit Top : + module Top : + input with : Clock + output unsigned : Clock + wire trireg : Clock + unsigned <= with + trireg <= with + +;CHECK: Verilog Rename + +;CHECK: input with$ : Clock +;CHECK: output unsigned$ : Clock +;CHECK: wire trireg$ : Clock +;CHECK: trireg$ <= with$ +;CHECK: unsigned$ <= with$ + +;CHECK: Done! diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir deleted file mode 100644 index 6eb341d7..00000000 --- a/test/passes/expand-whens/one-when.fir +++ /dev/null @@ -1,40 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - mem m : - data-type => UInt<1> - depth => 2 - read-latency => 0 - write-latency => 1 - wire i : UInt<1> - wire p : UInt<1> - wire j : UInt<1> - j <= UInt(1) - reg r : UInt<1>, clk, reset,i - - p <= j - when p : - - infer accessor a = m[i] - i <= a - infer accessor b = m[i] - b <= i - else : - infer accessor c = m[i] - i <= c - infer accessor d = m[i] - d <= i - infer accessor e = m[i] - when p : - p <= i - when e : - p <= p - r <= p - - -; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir deleted file mode 100644 index 38e02c5e..00000000 --- a/test/passes/expand-whens/two-when.fir +++ /dev/null @@ -1,40 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk - wire i : UInt<1> - i <= UInt(1) - wire p : UInt<1> - p <= UInt(1) - wire q : { x : UInt<1>, y : UInt<1> } - when p : - wire p2 : UInt<1> - p2 <= UInt(1) - when p2 : - infer accessor a = m[i] - q <= a - infer accessor b = m[i] - b <= q - else : - infer accessor c = m[i] - q <= c - infer accessor d = m[i] - d <= q - else : - wire p3 : UInt<1> - p3 <= UInt(1) - when p3 : - infer accessor w = m[i] - q <= w - infer accessor x = m[i] - x <= q - else : - infer accessor y = m[i] - q <= y - infer accessor z = m[i] - z <= q -; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index d2a09367..102a94ae 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -1,6 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * -; TODO Talk to Andrew about bit operations (and, or, etc.) on SInts ;CHECK: Infer Types circuit top : diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir index c3ec4921..319e87d5 100644 --- a/test/passes/jacktest/Stack.fir +++ b/test/passes/jacktest/Stack.fir @@ -17,7 +17,7 @@ circuit Stack : node T_30 = lt(sp, UInt<5>(16)) node T_31 = and(push, T_30) when T_31 : - write mport T_32 = stack_mem[sp],clk,UInt(1) + write mport T_32 = stack_mem[sp],clk T_32 <= dataIn node T_33 = addw(sp, UInt<1>(1)) sp <= T_33 diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir index 9b259d0f..5feb71bb 100644 --- a/test/passes/jacktest/Tbl.fir +++ b/test/passes/jacktest/Tbl.fir @@ -1,19 +1,21 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Done! -circuit Tbl : - module Tbl : - input i : UInt<16> - input d : UInt<16> + +circuit Tbl : + module Tbl : input clk : Clock - output o : UInt<16> - input we : UInt<1> - - cmem m : UInt<10>[256] - o <= UInt<1>(0) - when we : - write mport T_13 = m[i],clk,UInt(1) - node T_14 = bits(d, 9, 0) - T_13 <= T_14 - else : - read mport T_15 = m[i],clk - o <= T_15 + input reset : UInt<1> + output io : {flip wi : UInt<3>, flip ri : UInt<3>, flip we : UInt<1>, flip d : UInt<3>, o : UInt<3>} + + io.o <= UInt<1>("h00") + cmem m : UInt<3>[8] + infer mport T_12 = m[io.ri], clk + io.o <= T_12 + when io.we : + infer mport T_13 = m[io.wi], clk + T_13 <= io.d + node T_14 = eq(io.ri, io.wi) + when T_14 : + io.o <= io.d + skip + skip diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index eb823321..46f5a1c2 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s ; CHECK: Done! circuit Risc : module Risc : @@ -30,7 +30,7 @@ circuit Risc : out <= UInt<1>(0) rc <= UInt<1>(0) when isWr : - write mport T_55 = code[wrAddr],clk,UInt(1) + write mport T_55 = code[wrAddr],clk T_55 <= wrData else : when boot : pc <= UInt<1>(0) else : @@ -47,7 +47,7 @@ circuit Risc : node T_61 = eq(rci, UInt<8>(255)) when T_61 : valid <= UInt<1>(1) else : - write mport T_62 = file[rci],clk,UInt(1) + write mport T_62 = file[rci],clk T_62 <= rc node T_63 = addw(pc, UInt<1>(1)) pc <= T_63 diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 9821f69b..64a4a4b6 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -19,11 +19,11 @@ circuit top : j <= a[i] a[i] <= j -;CHECK: wire GEN : UInt<32> +;CHECK: wire GEN_0 : UInt<32> ;CHECK: wire GEN_1 : UInt<32> ;CHECK: wire GEN_2 : UInt<32> ;CHECK: wire GEN_3 : UInt<32> -;CHECK: j_x <= GEN +;CHECK: j_x <= GEN_0 ;CHECK: j_y <= GEN_3 ;CHECK: node GEN_4 = eqv(UInt("h0"), i) ;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) @@ -34,7 +34,7 @@ circuit top : ;CHECK: node GEN_7 = eqv(UInt("h1"), i) ;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) ;CHECK: node GEN_8 = eqv(UInt("h1"), i) -;CHECK: GEN <= mux(GEN_8, a_1_x, a_0_x) +;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x) ;CHECK: GEN_1 <= j_y ;CHECK: GEN_2 <= j_x ;CHECK: node GEN_9 = eqv(UInt("h1"), i) diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir index 4cf61462..ac3ef21e 100644 --- a/test/passes/lower-to-ground/test.fir +++ b/test/passes/lower-to-ground/test.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cdt 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ; CHECK: Done! circuit Top : diff --git a/test/passes/pull-muxes/Muxes.fir b/test/passes/pull-muxes/Muxes.fir new file mode 100644 index 00000000..295e3ca0 --- /dev/null +++ b/test/passes/pull-muxes/Muxes.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +circuit Top : + module Top : + input a : {f:UInt<3>[3]}[2] + input b : {f:UInt<3>[3]}[2] + input p : UInt<1> + input i : UInt<1> + node x = mux(p,mux(p,a[i],a[1]).f,b[i].f)[2] + + + +;CHECK: Pull Muxes +;CHECK: node x = mux(p, mux(p, a[i].f[2], a[1].f[2]), b[i].f[2]) +;CHECK: Finished Pull Muxes +;CHECK: Done! + + diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir index 13f9d8d6..e916bfa8 100644 --- a/test/passes/remove-accesses/bundle-vecs.fir +++ b/test/passes/remove-accesses/bundle-vecs.fir @@ -29,10 +29,10 @@ circuit top : ; CHECK: a[1].x <= UInt("h1") ; CHECK: a[1].y <= UInt("h1") ; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>} -; CHECK: wire GEN : UInt<32> -; CHECK: GEN <= a[0].x -; CHECK: when eqv(UInt("h1"), i) : GEN <= a[1].x -; CHECK: b.x <= GEN +; CHECK: wire GEN_0 : UInt<32> +; CHECK: GEN_0 <= a[0].x +; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x +; CHECK: b.x <= GEN_0 ; CHECK: wire GEN_1 : UInt<32> ; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1 ; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1 diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir index c7d00aff..b19c4130 100644 --- a/test/passes/remove-accesses/simple3.fir +++ b/test/passes/remove-accesses/simple3.fir @@ -12,10 +12,10 @@ circuit top : m[i] <= a a <= in -;CHECK: wire GEN : UInt<32> -;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN -;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN -;CHECK: GEN <= a +;CHECK: wire GEN_0 : UInt<32> +;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN_0 +;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN_0 +;CHECK: GEN_0 <= a ;CHECK: Finished Remove Accesses diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir index 4772c549..06ff7481 100644 --- a/test/passes/remove-accesses/simple4.fir +++ b/test/passes/remove-accesses/simple4.fir @@ -12,9 +12,9 @@ circuit top : m[1].y <= UInt("h1") m[i].x <= in.x -;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN -;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN -;CHECK: GEN <= in +;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN_0 +;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN_0 +;CHECK: GEN_0 <= in ;CHECK: Finished Remove Accesses ;CHECK: Done! diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir index 099f020c..0a1baed6 100644 --- a/test/passes/remove-accesses/simple5.fir +++ b/test/passes/remove-accesses/simple5.fir @@ -14,8 +14,8 @@ circuit top : o <= m[i] ;CHECK: when i : -;CHECK: GEN <= m[0] -;CHECK: when eqv(UInt("h1"), i) : GEN <= m[1] -;CHECK: o <= GEN +;CHECK: GEN_0 <= m[0] +;CHECK: when eqv(UInt("h1"), i) : GEN_0 <= m[1] +;CHECK: o <= GEN_0 ;CHECK: Finished Remove Accesses ;CHECK: Done! diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir index ae0d1ffd..6b084ed3 100644 --- a/test/passes/remove-accesses/simple8.fir +++ b/test/passes/remove-accesses/simple8.fir @@ -52,7 +52,7 @@ circuit top : wire T_114 : UInt<128> T_114 <= UInt<1>("h00") T_114 <= T_113 - write mport T_116 = T_84[waddr],clock,UInt(1) + write mport T_116 = T_84[waddr],clock T_116 <= T_114 skip node T_118 = neq(T_66, UInt<1>("h00")) @@ -90,7 +90,7 @@ circuit top : wire T_154 : UInt<128> T_154 <= UInt<1>("h00") T_154 <= T_153 - write mport T_156 = T_124[waddr],clock,UInt(1) + write mport T_156 = T_124[waddr],clock T_156 <= T_154 skip node T_158 = neq(T_66, UInt<1>("h00")) @@ -159,7 +159,7 @@ circuit top : wire T_241 : UInt<128> T_241 <= UInt<1>("h00") T_241 <= T_240 - write mport T_243 = T_211[waddr],clock,UInt(1) + write mport T_243 = T_211[waddr],clock T_243 <= T_241 skip node T_245 = neq(T_193, UInt<1>("h00")) @@ -197,7 +197,7 @@ circuit top : wire T_281 : UInt<128> T_281 <= UInt<1>("h00") T_281 <= T_280 - write mport T_283 = T_251[waddr],clock,UInt(1) + write mport T_283 = T_251[waddr],clock T_283 <= T_281 skip node T_285 = neq(T_193, UInt<1>("h00")) diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index 69e2b96e..e4d0da36 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -13,8 +13,8 @@ circuit Top : when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node GEN = subw(a, c) -;CHECK: node GEN_1 = bit(GEN, 3) +;CHECK: node GEN_0 = subw(a, c) +;CHECK: node GEN_1 = bit(GEN_0, 3) ;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd")) ;CHECK: node GEN_3 = addw(b, c) ;CHECK: node GEN_4 = addw(a, GEN_3) diff --git a/test/passes/to-verilog/rd-mem.fir b/test/passes/to-verilog/rd-mem.fir index 7146f026..59829777 100644 --- a/test/passes/to-verilog/rd-mem.fir +++ b/test/passes/to-verilog/rd-mem.fir @@ -18,36 +18,34 @@ circuit top : m.c.clk <= clk rdata <= m.c.data -; CHECK: module top( -; CHECK: output [31:0] rdata, -; CHECK: input [1:0] index, -; CHECK: input ren, -; CHECK: input clk, -; CHECK: ); -; CHECK: reg [31:0] m [0:3]; -; CHECK: wire [31:0] m_c_data; -; CHECK: wire [1:0] m_c_addr; -; CHECK: wire m_c_en; -; CHECK: wire m_c_clk; -; CHECK: reg [1:0] GEN; -; CHECK: reg GEN_1; -; CHECK: assign rdata = m_c_data -; CHECK: assign m_c_addr = index -; CHECK: assign m_c_en = ren -; CHECK: assign m_c_clk = clk -; CHECK: `ifndef SYNTHESIS -; CHECK: integer initvar; -; CHECK: initial begin -; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) -; CHECK: m[initvar] = {1{$random}}; -; CHECK: end -; CHECK: `endif -; CHECK: always @(posedge m_c_clk) begin -; CHECK: GEN <= m_c_addr -; CHECK: GEN_1 <= m_c_en -; CHECK: if(GEN_1) begin -; CHECK: m_c_data <= m[GEN] -; CHECK: end -; CHECK: end -; CHECK: endmodule +;CHECK: module top( +;CHECK: output [31:0] rdata, +;CHECK: input [1:0] index, +;CHECK: input ren, +;CHECK: input clk +;CHECK: ); +;CHECK: reg [31:0] m [0:3]; +;CHECK: wire [31:0] m_c_data; +;CHECK: wire [1:0] m_c_addr; +;CHECK: wire m_c_en; +;CHECK: wire m_c_clk; +;CHECK: reg [1:0] GEN_0; +;CHECK: reg GEN_1; +;CHECK: assign rdata = m_c_data; +;CHECK: assign m_c_addr = index; +;CHECK: assign m_c_en = ren; +;CHECK: assign m_c_clk = clk; +;CHECK: assign m_c_data = m[GEN_0]; +;CHECK: `ifndef SYNTHESIS +;CHECK: integer initvar; +;CHECK: initial begin +;CHECK: #0.002; +;CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +;CHECK: m[initvar] = {1{$random}}; +;CHECK: end +;CHECK: `endif +;CHECK: always @(posedge m_c_clk) begin +;CHECK: GEN_0 <= m_c_addr; +;CHECK: GEN_1 <= m_c_en; +;CHECK: end +;CHECK: endmodule |