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-rw-r--r--test/errors/high-form/Flip-Mem.fir2
-rw-r--r--test/errors/high-form/InstanceNotModule.fir2
-rw-r--r--test/errors/high-form/InvalidLOC.fir4
-rw-r--r--test/errors/high-form/InvalidSubexp.fir2
-rw-r--r--test/errors/high-form/NegUInt.fir4
-rw-r--r--test/errors/high-form/Prefix.fir2
-rw-r--r--test/errors/high-form/Top.fir2
-rw-r--r--test/errors/high-form/Unique.fir2
-rw-r--r--test/errors/high-form/WrongReset.fir2
-rw-r--r--test/passes/expand-connect-indexed/bundle-vecs.fir30
-rw-r--r--test/passes/expand-whens/bundle-init.fir8
-rw-r--r--test/passes/expand-whens/nested-whens.fir2
-rw-r--r--test/passes/lower-to-ground/accessor.fir12
-rw-r--r--test/passes/lower-to-ground/bundle-vecs.fir24
-rw-r--r--test/passes/lower-to-ground/bundle.fir56
-rw-r--r--test/passes/lower-to-ground/instance.fir8
-rw-r--r--test/passes/lower-to-ground/nested-vec.fir28
-rw-r--r--test/passes/lower-to-ground/register.fir12
18 files changed, 100 insertions, 102 deletions
diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 67fae14f..662fc6f1 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Memory m cannot be a bundle type with flips.
circuit Flip-Mem :
diff --git a/test/errors/high-form/InstanceNotModule.fir b/test/errors/high-form/InstanceNotModule.fir
index 3b228d37..7c4d152a 100644
--- a/test/errors/high-form/InstanceNotModule.fir
+++ b/test/errors/high-form/InstanceNotModule.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Module Top2 is not defined.
circuit Top :
diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir
index 5270577b..cbbb53a9 100644
--- a/test/errors/high-form/InvalidLOC.fir
+++ b/test/errors/high-form/InvalidLOC.fir
@@ -1,5 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
; CHECK: Invalid connect to an expression that is not a reference or a WritePort.
@@ -10,7 +9,6 @@ circuit Top :
module Top :
wire x : UInt
add(x,x) := UInt(1)
- Pad(x,?) := UInt(1)
Register(x,x) := UInt(1)
ReadPort(x,x,x) := UInt(1)
UInt(1) := UInt(1)
diff --git a/test/errors/high-form/InvalidSubexp.fir b/test/errors/high-form/InvalidSubexp.fir
index 85fad6fb..8116cc2f 100644
--- a/test/errors/high-form/InvalidSubexp.fir
+++ b/test/errors/high-form/InvalidSubexp.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Invalid index access to non-reference.
; CHECK: Invalid subfield access to non-reference.
diff --git a/test/errors/high-form/NegUInt.fir b/test/errors/high-form/NegUInt.fir
index a92da633..9050ac12 100644
--- a/test/errors/high-form/NegUInt.fir
+++ b/test/errors/high-form/NegUInt.fir
@@ -1,5 +1,5 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: UIntValue cannot be negative.
+; to run: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; to check: UIntValue cannot be negative.
circuit Top :
module Top :
diff --git a/test/errors/high-form/Prefix.fir b/test/errors/high-form/Prefix.fir
index 17be36f6..2f0a0247 100644
--- a/test/errors/high-form/Prefix.fir
+++ b/test/errors/high-form/Prefix.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Reference x$y and x share a prefix.
circuit Top :
diff --git a/test/errors/high-form/Top.fir b/test/errors/high-form/Top.fir
index 1d663c9c..1029d502 100644
--- a/test/errors/high-form/Top.fir
+++ b/test/errors/high-form/Top.fir
@@ -1,5 +1,5 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
; CHECK: A single module must be named Top.
circuit Top :
diff --git a/test/errors/high-form/Unique.fir b/test/errors/high-form/Unique.fir
index de95e6cd..26c4c7da 100644
--- a/test/errors/high-form/Unique.fir
+++ b/test/errors/high-form/Unique.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Reference x does not have a unique name.
; CHECK: Reference p does not have a unique name.
diff --git a/test/errors/high-form/WrongReset.fir b/test/errors/high-form/WrongReset.fir
index c936f0b3..adeadee6 100644
--- a/test/errors/high-form/WrongReset.fir
+++ b/test/errors/high-form/WrongReset.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Module Top has a reset that is not of type UInt<1>.
; CHECK: Module B has a reset that is not of type UInt<1>.
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 7922c278..901ab4e6 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
wire j : UInt
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a$0$x : UInt<32>
- ; CHECK: wire a$0$y : UInt<32>
- ; CHECK: wire a$1$x : UInt<32>
- ; CHECK: wire a$1$y : UInt<32>
+ ; CHECK: wire a_0_x : UInt<32>
+ ; CHECK: wire a_0_y : UInt<32>
+ ; CHECK: wire a_1_x : UInt<32>
+ ; CHECK: wire a_1_y : UInt<32>
accessor b = a[i]
- ; CHECK: wire b$x : UInt<32>
- ; CHECK: wire b$y : UInt<32>
- ; CHECK: b$x := a$0$x
- ; CHECK: node b$x#0 = i
- ; CHECK: when eq(b$x#0, UInt(1)) :
- ; CHECK: b$x := a$1$x
- ; CHECK: node b$y#0 = i
- ; CHECK: when eq(b$y#0, UInt(0)) :
- ; CHECK: a$0$y := b$y
- ; CHECK: when eq(b$y#0, UInt(1)) :
- ; CHECK: a$1$y := b$y
+ ; CHECK: wire b_x : UInt<32>
+ ; CHECK: wire b_y : UInt<32>
+ ; CHECK: b_x := a_0_x
+ ; CHECK: node b_x__0 = i
+ ; CHECK: when eq(b_x__0, UInt(1)) :
+ ; CHECK: b_x := a_1_x
+ ; CHECK: node b_y__0 = i
+ ; CHECK: when eq(b_y__0, UInt(0)) :
+ ; CHECK: a_0_y := b_y
+ ; CHECK: when eq(b_y__0, UInt(1)) :
+ ; CHECK: a_1_y := b_y
j := b.x
; CHECK: Finished Expand Indexed Connects
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 4f8c31e2..c51604eb 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -15,11 +15,11 @@ circuit top :
r.y := b
on-reset r := w
-; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1))
-; CHECK: r$y := Register(b, UInt(1))
+; CHECK: node r_x = Register(mux(reset, w_x, a), UInt(1))
+; CHECK: node r_y = Register(b, UInt(1))
; CHECK: a := UInt(1)
; CHECK: b := UInt(2)
-; CHECK: w$x := b
-; CHECK: w$y := mux(reset, r$y, a)
+; CHECK: w_x := b
+; CHECK: w_y := mux(reset, r_y, a)
; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index f7ac8337..21a6f24b 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -20,5 +20,5 @@ circuit top :
on-reset r := y
r := b
r := z
-; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
+; CHECK: node r = Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
; CHECK: Finished Expand Whens
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 29663234..14b55c63 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -7,19 +7,19 @@ circuit top :
wire j : UInt<32>
wire a : UInt<32>[4]
- ; CHECK: wire a$0 : UInt<32>
- ; CHECK: wire a$1 : UInt<32>
- ; CHECK: wire a$2 : UInt<32>
- ; CHECK: wire a$3 : UInt<32>
+ ; CHECK: wire a_0 : UInt<32>
+ ; CHECK: wire a_1 : UInt<32>
+ ; CHECK: wire a_2 : UInt<32>
+ ; CHECK: wire a_3 : UInt<32>
accessor b = a[i]
; CHECK: wire b : UInt<32>
- ; CHECK: b := (a$0 a$1 a$2 a$3)[i]
+ ; CHECK: b := (a_0 a_1 a_2 a_3)[i]
j := b
accessor c = a[i]
; CHECK: wire c : UInt<32>
- ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
+ ; CHECK: (a_0 a_1 a_2 a_3)[i] := c
c := j
mem p : UInt<32>[4]
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 0b9d9799..069314a3 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
wire j : { x : UInt<32>, flip y : UInt<32> }
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a$0$x : UInt<32>
- ; CHECK: wire a$0$y : UInt<32>
- ; CHECK: wire a$1$x : UInt<32>
- ; CHECK: wire a$1$y : UInt<32>
+ ; CHECK: wire a_0_x : UInt<32>
+ ; CHECK: wire a_0_y : UInt<32>
+ ; CHECK: wire a_1_x : UInt<32>
+ ; CHECK: wire a_1_y : UInt<32>
accessor b = a[i]
- ; CHECK: wire b$x : UInt<32>
- ; CHECK: wire b$y : UInt<32>
- ; CHECK: b$x := (a$0$x a$1$x)[i]
- ; CHECK: (a$0$y a$1$y)[i] := b$y
+ ; CHECK: wire b_x : UInt<32>
+ ; CHECK: wire b_y : UInt<32>
+ ; CHECK: b_x := (a_0_x a_1_x)[i]
+ ; CHECK: (a_0_y a_1_y)[i] := b_y
j := b
accessor c = a[i]
- ; CHECK: wire c$x : UInt<32>
- ; CHECK: wire c$y : UInt<32>
- ; CHECK: (a$0$x a$1$x)[i] := c$x
- ; CHECK: c$y := (a$0$y a$1$y)[i]
+ ; CHECK: wire c_x : UInt<32>
+ ; CHECK: wire c_y : UInt<32>
+ ; CHECK: (a_0_x a_1_x)[i] := c_x
+ ; CHECK: c_y := (a_0_y a_1_y)[i]
c := j
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index c0acfecd..e758acaf 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -17,37 +17,37 @@ circuit top :
;CHECK: Lower To Ground
;CHECK: circuit top :
;CHECK: module m :
-;CHECK: input a$x : UInt<5>
-;CHECK: output a$y : SInt<5>
-;CHECK: output b$x : UInt<5>
-;CHECK: input b$y : SInt<5>
+;CHECK: input a_x : UInt<5>
+;CHECK: output a_y : SInt<5>
+;CHECK: output b_x : UInt<5>
+;CHECK: input b_y : SInt<5>
;CHECK: input reset : UInt<1>
;CHECK: module top :
-;CHECK: input c$x$0 : UInt<5>
-;CHECK: input c$x$1 : UInt<5>
-;CHECK: input c$x$2 : UInt<5>
-;CHECK: input c$x$3 : UInt<5>
-;CHECK: input c$x$4 : UInt<5>
-;CHECK: output c$y$x$0 : UInt<5>
-;CHECK: output c$y$x$1 : UInt<5>
-;CHECK: output c$y$x$2 : UInt<5>
-;CHECK: input c$y$y : SInt<5>
+;CHECK: input c_x_0 : UInt<5>
+;CHECK: input c_x_1 : UInt<5>
+;CHECK: input c_x_2 : UInt<5>
+;CHECK: input c_x_3 : UInt<5>
+;CHECK: input c_x_4 : UInt<5>
+;CHECK: output c_y_x_0 : UInt<5>
+;CHECK: output c_y_x_1 : UInt<5>
+;CHECK: output c_y_x_2 : UInt<5>
+;CHECK: input c_y_y : SInt<5>
;CHECK: input reset : UInt<1>
-;CHECK: wire a$x : UInt<5>
-;CHECK: wire a$y : SInt<5>
-;CHECK: wire b$x : UInt<5>
-;CHECK: wire b$y : SInt<5>
-;CHECK: a$x := b$x
-;CHECK: b$y := a$y
+;CHECK: wire a_x : UInt<5>
+;CHECK: wire a_y : SInt<5>
+;CHECK: wire b_x : UInt<5>
+;CHECK: wire b_y : SInt<5>
+;CHECK: a_x := b_x
+;CHECK: b_y := a_y
;CHECK: inst i of m
;CHECK: i.reset := reset
-;CHECK: i.a$x := a$x
-;CHECK: a$y := i.a$y
-;CHECK: b$x := i.b$x
-;CHECK: i.b$y := b$y
-;CHECK: wire d$0 : UInt<5>
-;CHECK: wire d$1 : UInt<5>
-;CHECK: wire d$2 : UInt<5>
-;CHECK: wire d$3 : UInt<5>
-;CHECK: wire d$4 : UInt<5>
+;CHECK: i.a_x := a_x
+;CHECK: a_y := i.a_y
+;CHECK: b_x := i.b_x
+;CHECK: i.b_y := b_y
+;CHECK: wire d_0 : UInt<5>
+;CHECK: wire d_1 : UInt<5>
+;CHECK: wire d_2 : UInt<5>
+;CHECK: wire d_3 : UInt<5>
+;CHECK: wire d_4 : UInt<5>
;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 420c3c7c..57c68398 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -27,9 +27,9 @@ circuit top :
; CHECK: Lower To Ground
-; CHECK: connect$data@<g:f> := src@<g:m>.data@<g:m>
-; CHECK: src@<g:m>.ready@<g:f> := connect$ready@<g:m>
-; CHECK: snk@<g:m>.data@<g:f> := connect2$data@<g:m>
-; CHECK: connect2$ready@<g:f> := snk@<g:m>.ready@<g:m>
+; CHECK: connect_data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect_ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2_data@<g:m>
+; CHECK: connect2_ready@<g:f> := snk@<g:m>.ready@<g:m>
; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index b7915c5d..1a6ba2e8 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -8,29 +8,29 @@ circuit top :
wire k : { x : UInt<32>, y : UInt<32> }
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a$0$x : UInt<32>
- ; CHECK: wire a$0$y : UInt<32>
- ; CHECK: wire a$1$x : UInt<32>
- ; CHECK: wire a$1$y : UInt<32>
+ ; CHECK: wire a_0_x : UInt<32>
+ ; CHECK: wire a_0_y : UInt<32>
+ ; CHECK: wire a_1_x : UInt<32>
+ ; CHECK: wire a_1_y : UInt<32>
accessor b = a[i]
- ; CHECK: wire b$x : UInt<32>
- ; CHECK: wire b$y : UInt<32>
- ; CHECK: b$x := (a$0$x a$1$x)[i]
- ; CHECK: (a$0$y a$1$y)[i] := b$y
+ ; CHECK: wire b_x : UInt<32>
+ ; CHECK: wire b_y : UInt<32>
+ ; CHECK: b_x := (a_0_x a_1_x)[i]
+ ; CHECK: (a_0_y a_1_y)[i] := b_y
j := b
mem m : { x : UInt<32>, y : UInt<32> }[2]
- ; CHECK: mem m$x : UInt<32>[2]
- ; CHECK: mem m$y : UInt<32>[2]
+ ; CHECK: mem m_x : UInt<32>[2]
+ ; CHECK: mem m_y : UInt<32>[2]
accessor c = m[i] ; MALE
- ; CHECK: accessor c$x = m$x[i]
- ; CHECK: accessor c$y = m$y[i]
+ ; CHECK: accessor c_x = m_x[i]
+ ; CHECK: accessor c_y = m_y[i]
c := k
- ; CHECK: c$x := k$x
- ; CHECK: c$y := k$y
+ ; CHECK: c_x := k_x
+ ; CHECK: c_y := k_y
; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index a3c4f0ae..449204a3 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -11,11 +11,11 @@
wire q : { x : UInt, flip y : SInt }
on-reset r1 := q
- ; CHECK: reg r1$x : UInt
- ; CHECK: reg r1$y : SInt
- ; CHECK: wire q$x : UInt
- ; CHECK: wire q$y : SInt
- ; CHECK: on-reset r1$x := q$x
- ; CHECK: on-reset q$y := r1$y
+ ; CHECK: reg r1_x : UInt
+ ; CHECK: reg r1_y : SInt
+ ; CHECK: wire q_x : UInt
+ ; CHECK: wire q_y : SInt
+ ; CHECK: on-reset r1_x := q_x
+ ; CHECK: on-reset q_y := r1_y
; CHECK: Finished Lower To Ground
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 11:12:10 +0000