diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/chisel3/ALUTop.fir | 24 | ||||
| -rw-r--r-- | test/passes/to-verilog/gcd.fir | 2 |
2 files changed, 13 insertions, 13 deletions
diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir index 2cb4c32e..a6fdfd95 100644 --- a/test/chisel3/ALUTop.fir +++ b/test/chisel3/ALUTop.fir @@ -100,19 +100,19 @@ circuit ALUTop : node alu_op2 = mux(T_233, UInt<4>(11), T_232) alu_op := alu_op2 module ALUTop : - input io_B : UInt<32> - output io_out : UInt<32> - input io_A : UInt<32> - input io_opcode : UInt<7> - input io_funct : UInt<3> - input io_add_rshift_type : UInt<1> + input B : UInt<32> + output out : UInt<32> + input A : UInt<32> + input opcode : UInt<7> + input funct : UInt<3> + input add_rshift_type : UInt<1> inst alu of ALU inst alu_dec of ALUdec - alu_dec.opcode := io_opcode - alu_dec.funct := io_funct - alu_dec.add_rshift_type := io_add_rshift_type - alu.A := io_A - alu.B := io_B - io_out := alu.out + alu_dec.opcode := opcode + alu_dec.funct := funct + alu_dec.add_rshift_type := add_rshift_type + alu.A := A + alu.B := B + out := alu.out alu.alu_op := alu_dec.alu_op diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir index 170e7866..23a2d4f5 100644 --- a/test/passes/to-verilog/gcd.fir +++ b/test/passes/to-verilog/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cw tee %s.out | FileCheck %s ;CHECK: Verilog circuit top : |