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-rw-r--r--test/passes/infer-types/bundle.fir12
-rw-r--r--test/passes/infer-widths/dsh.fir3
-rw-r--r--test/passes/infer-widths/simple.fir4
-rw-r--r--test/passes/jacktest/MemorySearch.fir2
-rw-r--r--test/passes/jacktest/Mul.fir2
-rw-r--r--test/passes/jacktest/Rom.fir2
-rw-r--r--test/passes/jacktest/Stack.fir4
-rw-r--r--test/passes/jacktest/Tbl.fir4
-rw-r--r--test/passes/jacktest/risc.fir10
-rw-r--r--test/passes/lower-to-ground/accessor.fir8
-rw-r--r--test/passes/lower-to-ground/bundle-vecs.fir4
-rw-r--r--test/passes/lower-to-ground/nested-vec.fir4
-rw-r--r--test/passes/lower-to-ground/test.fir3
-rw-r--r--test/passes/resolve-genders/accessor.fir27
14 files changed, 63 insertions, 26 deletions
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 892103d2..6309b46f 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -4,9 +4,21 @@
circuit top :
module top :
wire z : { x : UInt, flip y: SInt}
+ z.x := UInt(1)
+ z.y := SInt(1)
node x = z.x ;CHECK: node x = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.x@<t:UInt>
node y = z.y ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt>
wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>>
+ a[0] := UInt(1)
+ a[1] := UInt(1)
+ a[2] := UInt(1)
+ a[3] := UInt(1)
+ a[4] := UInt(1)
+ a[5] := UInt(1)
+ a[6] := UInt(1)
+ a[7] := UInt(1)
+ a[8] := UInt(1)
+ a[9] := UInt(1)
node b = a[2] ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)]
; CHECK: Finished Infer Types
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir
index 6b683e56..08396978 100644
--- a/test/passes/infer-widths/dsh.fir
+++ b/test/passes/infer-widths/dsh.fir
@@ -11,6 +11,9 @@ circuit top :
wire b : SInt
wire c : UInt
wire d : SInt
+ x := UInt(1)
+ y := UInt(1)
+ z := SInt(1)
a := dshl(x,y)
b := dshl(z,y)
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 590515e7..6a50ae77 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -4,12 +4,16 @@
circuit top :
module top :
wire e : UInt<30>
+ e := UInt(1)
reg y : UInt
y := e
wire a : UInt<20>
+ a := UInt(1)
wire b : UInt<10>
+ b := UInt(1)
wire c : UInt
+ c := UInt(1)
wire z : UInt
z := mux(c,a,b)
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 1953e39b..59352162 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -17,7 +17,7 @@ circuit MemorySearch :
elts[4] := UInt<4>(2)
elts[5] := UInt<4>(5)
elts[6] := UInt<4>(13)
- accessor elt = elts[index]
+ infer accessor elt = elts[index]
node T_35 = bit-not(en)
node T_36 = eq(elt, target)
node T_37 = eq(index, UInt<3>(7))
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 58515110..14db8769 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -25,5 +25,5 @@ circuit Mul :
tbl[15] := UInt<4>(9)
node T_42 = shl(x, 2)
node T_43 = bit-or(T_42, y)
- accessor T_44 = tbl[T_43]
+ infer accessor T_44 = tbl[T_43]
z := T_44
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir
index ee417771..3c70c670 100644
--- a/test/passes/jacktest/Rom.fir
+++ b/test/passes/jacktest/Rom.fir
@@ -22,5 +22,5 @@ circuit Rom :
r[13] := UInt<5>(26)
r[14] := UInt<5>(28)
r[15] := UInt<5>(30)
- accessor T_39 = r[addr]
+ infer accessor T_39 = r[addr]
out := T_39
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 43f61827..4bce2bd4 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -17,7 +17,7 @@ circuit Stack :
node T_30 = lt(sp, UInt<5>(16))
node T_31 = bit-and(push, T_30)
when T_31 :
- accessor T_32 = stack_mem[sp]
+ infer accessor T_32 = stack_mem[sp]
T_32 := dataIn
node T_33 = add-wrap(sp, UInt<1>(1))
sp := T_33
@@ -30,6 +30,6 @@ circuit Stack :
node T_37 = gt(sp, UInt<1>(0))
when T_37 :
node T_38 = sub-wrap(sp, UInt<1>(1))
- accessor T_39 = stack_mem[T_38]
+ infer accessor T_39 = stack_mem[T_38]
out := T_39
dataOut := out
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index 4e0e954c..f315aaa9 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -10,9 +10,9 @@ circuit Tbl :
cmem m : UInt<10>[256]
o := UInt<1>(0)
when we :
- accessor T_13 = m[i]
+ infer accessor T_13 = m[i]
node T_14 = bits(d, 9, 0)
T_13 := T_14
else :
- accessor T_15 = m[i]
+ infer accessor T_15 = m[i]
o := T_15
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 4d02bcf7..21030448 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -13,23 +13,23 @@ circuit Risc :
cmem code : UInt<32>[256]
reg pc : UInt<8>
on-reset pc := UInt<8>(0)
- accessor inst = code[pc]
+ infer accessor inst = code[pc]
node op = bits(inst, 31, 24)
node rci = bits(inst, 23, 16)
node rai = bits(inst, 15, 8)
node rbi = bits(inst, 7, 0)
node T_51 = eq(rai, UInt<1>(0))
- accessor T_52 = file[rai]
+ infer accessor T_52 = file[rai]
node ra = mux(T_51, UInt<1>(0), T_52)
node T_53 = eq(rbi, UInt<1>(0))
- accessor T_54 = file[rbi]
+ infer accessor T_54 = file[rbi]
node rb = mux(T_53, UInt<1>(0), T_54)
wire rc : UInt<32>
valid := UInt<1>(0)
out := UInt<1>(0)
rc := UInt<1>(0)
when isWr :
- accessor T_55 = code[wrAddr]
+ infer accessor T_55 = code[wrAddr]
T_55 := wrData
else : when boot : pc := UInt<1>(0)
else :
@@ -46,7 +46,7 @@ circuit Risc :
node T_61 = eq(rci, UInt<8>(255))
when T_61 : valid := UInt<1>(1)
else :
- accessor T_62 = file[rci]
+ infer accessor T_62 = file[rci]
T_62 := rc
node T_63 = add-wrap(pc, UInt<1>(1))
pc := T_63
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 8fe1bc52..cede6f43 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -12,21 +12,21 @@ circuit top :
; CHECK: wire a$2 : UInt<32>
; CHECK: wire a$3 : UInt<32>
- accessor b = a[i]
+ infer accessor b = a[i]
; CHECK: wire b : UInt<32>
; CHECK: b := (a$0 a$1 a$2 a$3)[i]
j := b
- accessor c = a[i]
+ infer accessor c = a[i]
; CHECK: wire c : UInt<32>
; CHECK: (a$0 a$1 a$2 a$3)[i] := c
c := j
cmem p : UInt<32>[4]
- accessor t = p[i]
+ infer accessor t = p[i]
; CHECK: accessor t = p[i]
j := t
- accessor r = p[i]
+ infer accessor r = p[i]
; CHECK: accessor r = p[i]
r := j
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 0b9d9799..e71e9104 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -12,14 +12,14 @@ circuit top :
; CHECK: wire a$1$x : UInt<32>
; CHECK: wire a$1$y : UInt<32>
- accessor b = a[i]
+ infer accessor b = a[i]
; CHECK: wire b$x : UInt<32>
; CHECK: wire b$y : UInt<32>
; CHECK: b$x := (a$0$x a$1$x)[i]
; CHECK: (a$0$y a$1$y)[i] := b$y
j := b
- accessor c = a[i]
+ infer accessor c = a[i]
; CHECK: wire c$x : UInt<32>
; CHECK: wire c$y : UInt<32>
; CHECK: (a$0$x a$1$x)[i] := c$x
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index c39850f4..a2eb1215 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -13,7 +13,7 @@ circuit top :
; CHECK: wire a$1$x : UInt<32>
; CHECK: wire a$1$y : UInt<32>
- accessor b = a[i]
+ infer accessor b = a[i]
; CHECK: wire b$x : UInt<32>
; CHECK: wire b$y : UInt<32>
; CHECK: b$x := (a$0$x a$1$x)[i]
@@ -24,7 +24,7 @@ circuit top :
; CHECK: cmem m$x : UInt<32>[2]
; CHECK: cmem m$y : UInt<32>[2]
- accessor c = m[i] ; MALE
+ infer accessor c = m[i] ; MALE
; CHECK: accessor c$x = m$x[i]
; CHECK: accessor c$y = m$y[i]
diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir
index 7fcf0013..7e123fc3 100644
--- a/test/passes/lower-to-ground/test.fir
+++ b/test/passes/lower-to-ground/test.fir
@@ -4,10 +4,13 @@
circuit Top :
module Queue :
output out : {valid : UInt<1>, flip ready : UInt<1>}
+ out.valid := UInt(1)
module Top :
output this : {out : {valid : UInt<1>, flip ready : UInt<1>}}
inst queue of Queue
this.out := queue.out
wire w : { x : UInt<5>, flip y : UInt<5>}
+ w.x := UInt(1)
wire a : UInt<5>
+ a := UInt(1)
w.y := a
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 41aea1f4..8a86868b 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -4,16 +4,31 @@
circuit top :
module top :
wire m : UInt<32>[2][2][2]
+ m[0][0][0] := UInt(1)
+ m[1][0][0] := UInt(1)
+ m[0][1][0] := UInt(1)
+ m[1][1][0] := UInt(1)
+ m[0][0][1] := UInt(1)
+ m[1][0][1] := UInt(1)
+ m[0][1][1] := UInt(1)
+ m[1][1][1] := UInt(1)
wire i : UInt
- accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
- accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
- accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
+ i := UInt(1)
+ infer accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
+ infer accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
+ infer accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
wire j : UInt
j := c
- accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
- accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
- accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
+ infer accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
+ x[0][0] := UInt(1)
+ x[1][0] := UInt(1)
+ x[0][1] := UInt(1)
+ x[1][1] := UInt(1)
+ infer accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
+ y[0] := UInt(1)
+ y[1] := UInt(1)
+ infer accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
z := j
; CHECK: Finished Resolve Genders
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 20:13:30 +0000