diff options
Diffstat (limited to 'test/passes/to-verilog')
| -rw-r--r-- | test/passes/to-verilog/gcd.fir | 8 | ||||
| -rw-r--r-- | test/passes/to-verilog/shr.fir | 9 |
2 files changed, 11 insertions, 6 deletions
diff --git a/test/passes/to-verilog/gcd.fir b/test/passes/to-verilog/gcd.fir index cadd9ec8..5a50ddd1 100644 --- a/test/passes/to-verilog/gcd.fir +++ b/test/passes/to-verilog/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q <= subw(x, y) + q <= tail(sub(x, y),1) module gcd : input clk : Clock input reset : UInt<1> @@ -14,8 +14,10 @@ circuit top : input b : UInt<16> input e : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/to-verilog/shr.fir b/test/passes/to-verilog/shr.fir index d8e889da..6921e74e 100644 --- a/test/passes/to-verilog/shr.fir +++ b/test/passes/to-verilog/shr.fir @@ -16,9 +16,12 @@ circuit HellaCache : inst dtlb of TLB_60 poison init : {addr : UInt<40>} - reg s1_req : {addr : UInt<40>}, clock, reset, init - reg s2_req : {addr : UInt<40>}, clock, reset, init - reg s1_clk_en : UInt<1>, clock, reset, UInt(0) + reg s1_req : {addr : UInt<40>}, clock with : + reset => ( reset, init) + reg s2_req : {addr : UInt<40>}, clock with : + reset => ( reset, init) + reg s1_clk_en : UInt<1>, clock with : + reset => ( reset, UInt(0)) node T_928 = bits(s1_req.addr, 11, 0) node s1_addr = cat(dtlb.resp.ppn, T_928) |