diff options
Diffstat (limited to 'test/passes/to-verilog/wr-mem.fir')
| -rw-r--r-- | test/passes/to-verilog/wr-mem.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir index 7641e894..b21491aa 100644 --- a/test/passes/to-verilog/wr-mem.fir +++ b/test/passes/to-verilog/wr-mem.fir @@ -10,7 +10,7 @@ circuit top : smem m : UInt<32>[4],clk write accessor c = m[index] when wen : - c := wdata + c <= wdata ; CHECK: module top( ; CHECK: input [31:0] wdata, |