diff options
Diffstat (limited to 'test/passes/to-verilog/rdwr-mem.fir')
| -rw-r--r-- | test/passes/to-verilog/rdwr-mem.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/to-verilog/rdwr-mem.fir b/test/passes/to-verilog/rdwr-mem.fir index 667d831f..d056ecf6 100644 --- a/test/passes/to-verilog/rdwr-mem.fir +++ b/test/passes/to-verilog/rdwr-mem.fir @@ -12,9 +12,9 @@ circuit top : smem m : UInt<32>[4],clk rdwr accessor c = m[index] when ren : - rdata := c + rdata <= c when wen : - c := wdata + c <= wdata ; CHECK: module top( |