1 files changed, 12 insertions, 0 deletions
diff --git a/test/passes/to-verilog/mem.fir b/test/passes/to-verilog/mem.fir
new file mode 100644
index 00000000..0d0e0e5f
--- /dev/null
+++ b/test/passes/to-verilog/mem.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s
+
+;CHECK: reg  [29:0] m [0:127];
+circuit top :
+   module top :
+      input clk : Clock
+      output read : UInt<30>
+      cmem m : UInt<30>[128], clk
+      read accessor x = m[UInt(0)]
+      read := x
+      
+