diff options
Diffstat (limited to 'test/passes/split-exp')
| -rw-r--r-- | test/passes/split-exp/gcd.fir | 8 | ||||
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 23 |
2 files changed, 19 insertions, 12 deletions
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index e651f41a..4b42d007 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q <= subw(x, y) + q <= tail(sub(x, y),1) module gcd : input clk : Clock input reset : UInt<1> @@ -14,8 +14,10 @@ circuit top : input b : UInt<16> input e : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset,UInt(0) - reg y : UInt,clk,reset,UInt(42) + reg x : UInt,clk with : + reset => (reset,UInt(0)) + reg y : UInt,clk with : + reset => (reset,UInt(42)) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index e4d0da36..06d1463d 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -9,16 +9,21 @@ circuit Top : input b : UInt<10> input c : UInt<10> - reg out : UInt<10>,clk,p,a + reg out : UInt<10>,clk with : + reset => (p,a) - when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) + when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1)) -;CHECK: node GEN_0 = subw(a, c) -;CHECK: node GEN_1 = bit(GEN_0, 3) -;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd")) -;CHECK: node GEN_3 = addw(b, c) -;CHECK: node GEN_4 = addw(a, GEN_3) -;CHECK: node GEN_5 = subw(c, b) -;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out) +;CHECK: node GEN_0 = sub(a, c) +;CHECK: node GEN_1 = tail(GEN_0, 1) +;CHECK: node GEN_2 = bits(GEN_1, 3, 3) +;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd")) +;CHECK: node GEN_4 = add(b, c) +;CHECK: node GEN_5 = tail(GEN_4, 1) +;CHECK: node GEN_6 = add(a, GEN_5) +;CHECK: node GEN_7 = tail(GEN_6, 1) +;CHECK: node GEN_8 = sub(c, b) +;CHECK: node GEN_9 = tail(GEN_8, 1) +;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out) ;CHECK: Finished Split Expressions |