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-rw-r--r--test/passes/split-exp/split-in-when.fir23
1 files changed, 14 insertions, 9 deletions
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir
index e4d0da36..06d1463d 100644
--- a/test/passes/split-exp/split-in-when.fir
+++ b/test/passes/split-exp/split-in-when.fir
@@ -9,16 +9,21 @@ circuit Top :
input b : UInt<10>
input c : UInt<10>
- reg out : UInt<10>,clk,p,a
+ reg out : UInt<10>,clk with :
+ reset => (p,a)
- when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b))
+ when bits(tail(sub(a,c),1),3,3) : out <= mux(eq(bits(UInt(32),4,0),UInt(13)),tail(add(a,tail(add(b,c),1)),1),tail(sub(c,b),1))
-;CHECK: node GEN_0 = subw(a, c)
-;CHECK: node GEN_1 = bit(GEN_0, 3)
-;CHECK: node GEN_2 = eqv(UInt("h0"), UInt("hd"))
-;CHECK: node GEN_3 = addw(b, c)
-;CHECK: node GEN_4 = addw(a, GEN_3)
-;CHECK: node GEN_5 = subw(c, b)
-;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out)
+;CHECK: node GEN_0 = sub(a, c)
+;CHECK: node GEN_1 = tail(GEN_0, 1)
+;CHECK: node GEN_2 = bits(GEN_1, 3, 3)
+;CHECK: node GEN_3 = eq(UInt("h0"), UInt("hd"))
+;CHECK: node GEN_4 = add(b, c)
+;CHECK: node GEN_5 = tail(GEN_4, 1)
+;CHECK: node GEN_6 = add(a, GEN_5)
+;CHECK: node GEN_7 = tail(GEN_6, 1)
+;CHECK: node GEN_8 = sub(c, b)
+;CHECK: node GEN_9 = tail(GEN_8, 1)
+;CHECK: out <= mux(GEN_2, mux(GEN_3, GEN_7, GEN_9), out)
;CHECK: Finished Split Expressions