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-rw-r--r--test/passes/split-exp/print-args.fir14
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diff --git a/test/passes/split-exp/print-args.fir b/test/passes/split-exp/print-args.fir
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index df21949d..00000000
--- a/test/passes/split-exp/print-args.fir
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@@ -1,14 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-; CHECK: Split Expressions
-; CHECK: node GEN_0 = and(a, b)
-; CHECK: printf(clk, UInt<1>("h1"), "%d\n", GEN_0)
-
-circuit Bug :
- module Bug :
- input clk : Clock
- input a : UInt<1>
- input b : UInt<1>
-
- printf(clk, UInt<1>(1), "%d\n", and(a, b))
-