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-rw-r--r--test/passes/split-exp/gcd.fir18
1 files changed, 9 insertions, 9 deletions
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index 75efa2f8..71835204 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -8,15 +8,15 @@ circuit top :
output q : UInt
q := sub-wrap-uu(x, y)
module gcd :
- input a : UInt(16)
- input b : UInt(16)
- input e : UInt(1)
- output z : UInt(16)
- output v : UInt(1)
+ input a : UInt<16>
+ input b : UInt<16>
+ input e : UInt<1>
+ output z : UInt<16>
+ output v : UInt<1>
reg x : UInt
reg y : UInt
- x.init := UInt(0)
- y.init := UInt(42)
+ on-reset x := UInt(0)
+ on-reset y := UInt(42)
when gt-uu(x, y) :
inst s of subtracter
s.x := x
@@ -33,8 +33,8 @@ circuit top :
v := eq-uu(v, UInt(0))
z := x
module top :
- input a : UInt(16)
- input b : UInt(16)
+ input a : UInt<16>
+ input b : UInt<16>
output z : UInt
inst i of gcd
i.a := a