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Diffstat (limited to 'test/passes/remove-accesses/simple4.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple4.fir | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir new file mode 100644 index 00000000..4772c549 --- /dev/null +++ b/test/passes/remove-accesses/simple4.fir @@ -0,0 +1,22 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Remove Accesses +circuit top : + module top : + input in : {x : UInt<32>, y : UInt<32>} + input i : UInt<1> + wire m : {x : UInt<32>, y : UInt<32>}[2] + m[0].x <= UInt("h1") + m[0].y <= UInt("h1") + m[1].x <= UInt("h1") + m[1].y <= UInt("h1") + m[i].x <= in.x + +;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN +;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN +;CHECK: GEN <= in +;CHECK: Finished Remove Accesses +;CHECK: Done! + + + |