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-rw-r--r--test/passes/remove-accesses/bundle-vecs.fir6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir
index e916bfa8..e618892e 100644
--- a/test/passes/remove-accesses/bundle-vecs.fir
+++ b/test/passes/remove-accesses/bundle-vecs.fir
@@ -31,11 +31,11 @@ circuit top :
; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>}
; CHECK: wire GEN_0 : UInt<32>
; CHECK: GEN_0 <= a[0].x
-; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x
+; CHECK: when eq(UInt("h1"), i) : GEN_0 <= a[1].x
; CHECK: b.x <= GEN_0
; CHECK: wire GEN_1 : UInt<32>
-; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1
-; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1
+; CHECK: when eq(UInt("h0"), i) : a[0].y <= GEN_1
+; CHECK: when eq(UInt("h1"), i) : a[1].y <= GEN_1
; CHECK: GEN_1 <= b.y
; CHECK: j <= b.x
; CHECK: b.y <= UInt("h1")