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-rw-r--r--test/passes/lower-to-ground/accessor.fir16
-rw-r--r--test/passes/lower-to-ground/bundle-vecs.fir24
-rw-r--r--test/passes/lower-to-ground/bundle.fir56
-rw-r--r--test/passes/lower-to-ground/instance.fir8
-rw-r--r--test/passes/lower-to-ground/nested-vec.fir28
-rw-r--r--test/passes/lower-to-ground/register.fir16
6 files changed, 74 insertions, 74 deletions
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 4858fafb..19b6ac96 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -8,27 +8,27 @@ circuit top :
wire j : UInt<32>
wire a : UInt<32>[4]
- ; CHECK: wire a_0 : UInt<32>
- ; CHECK: wire a_1 : UInt<32>
- ; CHECK: wire a_2 : UInt<32>
- ; CHECK: wire a_3 : UInt<32>
+ ; CHECK: wire a{{[_$]+}}0 : UInt<32>
+ ; CHECK: wire a{{[_$]+}}1 : UInt<32>
+ ; CHECK: wire a{{[_$]+}}2 : UInt<32>
+ ; CHECK: wire a{{[_$]+}}3 : UInt<32>
infer accessor b = a[i]
; CHECK: wire b : UInt<32>
- ; CHECK: b := (a_0 a_1 a_2 a_3)[i]
+ ; CHECK: b := (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i]
j := b
infer accessor c = a[i]
; CHECK: wire c : UInt<32>
- ; CHECK: (a_0 a_1 a_2 a_3)[i] := c
+ ; CHECK: (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] := c
c := j
cmem p : UInt<32>[4],clk
infer accessor t = p[i]
- ; CHECK: accessor t = p[i]
+ ; CHECK: read accessor t = p[i]
j := t
infer accessor r = p[i]
- ; CHECK: accessor r = p[i]
+ ; CHECK: write accessor r = p[i]
r := j
; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index ebf81093..fb1c8320 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
wire j : { x : UInt<32>, flip y : UInt<32> }
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a_0_x : UInt<32>
- ; CHECK: wire a_0_y : UInt<32>
- ; CHECK: wire a_1_x : UInt<32>
- ; CHECK: wire a_1_y : UInt<32>
+ ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32>
+ ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32>
+ ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32>
+ ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32>
infer accessor b = a[i]
- ; CHECK: wire b_x : UInt<32>
- ; CHECK: wire b_y : UInt<32>
- ; CHECK: b_x := (a_0_x a_1_x)[i]
- ; CHECK: (a_0_y a_1_y)[i] := b_y
+ ; CHECK: wire b{{[_$]+}}x : UInt<32>
+ ; CHECK: wire b{{[_$]+}}y : UInt<32>
+ ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i]
+ ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y
j := b
infer accessor c = a[i]
- ; CHECK: wire c_x : UInt<32>
- ; CHECK: wire c_y : UInt<32>
- ; CHECK: (a_0_x a_1_x)[i] := c_x
- ; CHECK: c_y := (a_0_y a_1_y)[i]
+ ; CHECK: wire c{{[_$]+}}x : UInt<32>
+ ; CHECK: wire c{{[_$]+}}y : UInt<32>
+ ; CHECK: (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] := c{{[_$]+}}x
+ ; CHECK: c{{[_$]+}}y := (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i]
c := j
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index 7c11cbc5..83318e10 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -17,34 +17,34 @@ circuit top :
;CHECK: Lower To Ground
;CHECK: circuit top :
;CHECK: module m :
-;CHECK: input a_x : UInt<5>
-;CHECK: output a_y : SInt<5>
-;CHECK: output b_x : UInt<5>
-;CHECK: input b_y : SInt<5>
+;CHECK: input a{{[_$]+}}x : UInt<5>
+;CHECK: output a{{[_$]+}}y : SInt<5>
+;CHECK: output b{{[_$]+}}x : UInt<5>
+;CHECK: input b{{[_$]+}}y : SInt<5>
;CHECK: module top :
-;CHECK: input c_x_0 : UInt<5>
-;CHECK: input c_x_1 : UInt<5>
-;CHECK: input c_x_2 : UInt<5>
-;CHECK: input c_x_3 : UInt<5>
-;CHECK: input c_x_4 : UInt<5>
-;CHECK: output c_y_x_0 : UInt<5>
-;CHECK: output c_y_x_1 : UInt<5>
-;CHECK: output c_y_x_2 : UInt<5>
-;CHECK: input c_y_y : SInt<5>
-;CHECK: wire a_x : UInt<5>
-;CHECK: wire a_y : SInt<5>
-;CHECK: wire b_x : UInt<5>
-;CHECK: wire b_y : SInt<5>
-;CHECK: a_x := b_x
-;CHECK: b_y := a_y
+;CHECK: input c{{[_$]+}}x{{[_$]+}}0 : UInt<5>
+;CHECK: input c{{[_$]+}}x{{[_$]+}}1 : UInt<5>
+;CHECK: input c{{[_$]+}}x{{[_$]+}}2 : UInt<5>
+;CHECK: input c{{[_$]+}}x{{[_$]+}}3 : UInt<5>
+;CHECK: input c{{[_$]+}}x{{[_$]+}}4 : UInt<5>
+;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}0 : UInt<5>
+;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}1 : UInt<5>
+;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}2 : UInt<5>
+;CHECK: input c{{[_$]+}}y{{[_$]+}}y : SInt<5>
+;CHECK: wire a{{[_$]+}}x : UInt<5>
+;CHECK: wire a{{[_$]+}}y : SInt<5>
+;CHECK: wire b{{[_$]+}}x : UInt<5>
+;CHECK: wire b{{[_$]+}}y : SInt<5>
+;CHECK: a{{[_$]+}}x := b{{[_$]+}}x
+;CHECK: b{{[_$]+}}y := a{{[_$]+}}y
;CHECK: inst i of m
-;CHECK: i.a_x := a_x
-;CHECK: a_y := i.a_y
-;CHECK: b_x := i.b_x
-;CHECK: i.b_y := b_y
-;CHECK: wire d_0 : UInt<5>
-;CHECK: wire d_1 : UInt<5>
-;CHECK: wire d_2 : UInt<5>
-;CHECK: wire d_3 : UInt<5>
-;CHECK: wire d_4 : UInt<5>
+;CHECK: i.a{{[_$]+}}x := a{{[_$]+}}x
+;CHECK: a{{[_$]+}}y := i.a{{[_$]+}}y
+;CHECK: b{{[_$]+}}x := i.b{{[_$]+}}x
+;CHECK: i.b{{[_$]+}}y := b{{[_$]+}}y
+;CHECK: wire d{{[_$]+}}0 : UInt<5>
+;CHECK: wire d{{[_$]+}}1 : UInt<5>
+;CHECK: wire d{{[_$]+}}2 : UInt<5>
+;CHECK: wire d{{[_$]+}}3 : UInt<5>
+;CHECK: wire d{{[_$]+}}4 : UInt<5>
;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 57c68398..cc8c07e6 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -27,9 +27,9 @@ circuit top :
; CHECK: Lower To Ground
-; CHECK: connect_data@<g:f> := src@<g:m>.data@<g:m>
-; CHECK: src@<g:m>.ready@<g:f> := connect_ready@<g:m>
-; CHECK: snk@<g:m>.data@<g:f> := connect2_data@<g:m>
-; CHECK: connect2_ready@<g:f> := snk@<g:m>.ready@<g:m>
+; CHECK: connect{{[_$]+}}data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect{{[_$]+}}ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2{{[_$]+}}data@<g:m>
+; CHECK: connect2{{[_$]+}}ready@<g:f> := snk@<g:m>.ready@<g:m>
; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 1f38d10e..fa149ffc 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -9,29 +9,29 @@ circuit top :
wire k : { x : UInt<32>, y : UInt<32> }
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
- ; CHECK: wire a_0_x : UInt<32>
- ; CHECK: wire a_0_y : UInt<32>
- ; CHECK: wire a_1_x : UInt<32>
- ; CHECK: wire a_1_y : UInt<32>
+ ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32>
+ ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32>
+ ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32>
+ ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32>
infer accessor b = a[i]
- ; CHECK: wire b_x : UInt<32>
- ; CHECK: wire b_y : UInt<32>
- ; CHECK: b_x := (a_0_x a_1_x)[i]
- ; CHECK: (a_0_y a_1_y)[i] := b_y
+ ; CHECK: wire b{{[_$]+}}x : UInt<32>
+ ; CHECK: wire b{{[_$]+}}y : UInt<32>
+ ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i]
+ ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y
j := b
cmem m : { x : UInt<32>, y : UInt<32> }[2],clk
- ; CHECK: cmem m_x : UInt<32>[2]
- ; CHECK: cmem m_y : UInt<32>[2]
+ ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2]
+ ; CHECK: cmem m{{[_$]+}}y : UInt<32>[2]
infer accessor c = m[i] ; MALE
- ; CHECK: accessor c_x = m_x[i]
- ; CHECK: accessor c_y = m_y[i]
+ ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i]
+ ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i]
c := k
- ; CHECK: c_x := k_x
- ; CHECK: c_y := k_y
+ ; CHECK: c{{[_$]+}}x := k{{[_$]+}}x
+ ; CHECK: c{{[_$]+}}y := k{{[_$]+}}y
; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index b045aadc..63519cac 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -9,15 +9,15 @@
input reset : UInt<1>
output z : UInt
- reg r1 : { x : UInt, flip y : SInt },clk,reset
- wire q : { x : UInt, flip y : SInt }
+ reg r1 : { x : UInt, y : SInt },clk,reset
+ wire q : { x : UInt, y : SInt }
onreset r1 := q
- ; CHECK: reg r1_x : UInt
- ; CHECK: reg r1_y : SInt
- ; CHECK: wire q_x : UInt
- ; CHECK: wire q_y : SInt
- ; CHECK: onreset r1_x := q_x
- ; CHECK: onreset q_y := r1_y
+ ; CHECK: reg r1{{[_$]+}}x : UInt
+ ; CHECK: reg r1{{[_$]+}}y : SInt
+ ; CHECK: wire q{{[_$]+}}x : UInt
+ ; CHECK: wire q{{[_$]+}}y : SInt
+ ; CHECK: onreset r1{{[_$]+}}x := q{{[_$]+}}x
+ ; CHECK: onreset r1{{[_$]+}}y := q{{[_$]+}}y
; CHECK: Finished Lower To Ground
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 11:14:49 +0000