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-rw-r--r--test/passes/lower-to-ground/register.fir6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 23ac8ac3..ecc427d9 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -3,13 +3,13 @@
; CHECK: Lower To Ground
circuit top :
module top :
- input a : UInt(16)
- input b : UInt(16)
+ input a : UInt<16>
+ input b : UInt<16>
output z : UInt
reg r1 : { x : UInt, flip y : SInt }
wire q : { x : UInt, flip y : SInt }
- r1.init := q
+ on-reset r1 := q
; CHECK: reg r1$x : UInt
; CHECK: reg r1$y : SInt