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-rw-r--r--test/passes/lower-to-ground/bundle.fir26
1 files changed, 18 insertions, 8 deletions
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index ccf942ee..b2ea2d63 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -4,6 +4,8 @@ circuit top :
module m :
input a : { x : UInt<5>, flip y: SInt<5>}
output b : { x : UInt<5>, flip y: SInt<5>}
+ a.y <= UInt(0)
+ b.x <= UInt(0)
module top :
input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } }
wire a : { x : UInt<5>, flip y : SInt<5>}
@@ -13,8 +15,16 @@ circuit top :
i.a <= a
b <= i.b
wire d : UInt<5>[5]
+ d[0] <= UInt(0)
+ d[1] <= UInt(0)
+ d[2] <= UInt(0)
+ d[3] <= UInt(0)
+ d[4] <= UInt(0)
+ c.y.x[0] <= UInt(0)
+ c.y.x[1] <= UInt(0)
+ c.y.x[2] <= UInt(0)
-;CHECK: Lower To Ground
+;CHECK: Lower Types
;CHECK: circuit top :
;CHECK: module m :
;CHECK: input a{{[_$]+}}x : UInt<5>
@@ -35,16 +45,16 @@ circuit top :
;CHECK: wire a{{[_$]+}}y : SInt<5>
;CHECK: wire b{{[_$]+}}x : UInt<5>
;CHECK: wire b{{[_$]+}}y : SInt<5>
-;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x
-;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y
;CHECK: inst i of m
-;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x
-;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y
-;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x
-;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y
;CHECK: wire d{{[_$]+}}0 : UInt<5>
;CHECK: wire d{{[_$]+}}1 : UInt<5>
;CHECK: wire d{{[_$]+}}2 : UInt<5>
;CHECK: wire d{{[_$]+}}3 : UInt<5>
;CHECK: wire d{{[_$]+}}4 : UInt<5>
-;CHECK: Finished Lower To Ground
+;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x
+;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y
+;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x
+;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y
+;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x
+;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y
+;CHECK: Finished Lower Types