diff options
Diffstat (limited to 'test/passes/lower-to-ground/bundle-vecs.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 64a4a4b6..c42766ad 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -25,19 +25,19 @@ circuit top : ;CHECK: wire GEN_3 : UInt<32> ;CHECK: j_x <= GEN_0 ;CHECK: j_y <= GEN_3 -;CHECK: node GEN_4 = eqv(UInt("h0"), i) +;CHECK: node GEN_4 = eq(UInt("h0"), i) ;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) -;CHECK: node GEN_5 = eqv(UInt("h0"), i) +;CHECK: node GEN_5 = eq(UInt("h0"), i) ;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0")) -;CHECK: node GEN_6 = eqv(UInt("h1"), i) +;CHECK: node GEN_6 = eq(UInt("h1"), i) ;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0")) -;CHECK: node GEN_7 = eqv(UInt("h1"), i) +;CHECK: node GEN_7 = eq(UInt("h1"), i) ;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) -;CHECK: node GEN_8 = eqv(UInt("h1"), i) +;CHECK: node GEN_8 = eq(UInt("h1"), i) ;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x) ;CHECK: GEN_1 <= j_y ;CHECK: GEN_2 <= j_x -;CHECK: node GEN_9 = eqv(UInt("h1"), i) +;CHECK: node GEN_9 = eq(UInt("h1"), i) ;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y) ; CHECK: Finished Lower Types |