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-rw-r--r--test/passes/jacktest/MemorySearch.fir50
-rw-r--r--test/passes/jacktest/RegisterVecShift.fir50
-rw-r--r--test/passes/jacktest/SIntOps.fir32
-rw-r--r--test/passes/jacktest/Tlb.fir12
-rw-r--r--test/passes/jacktest/UIntOps.fir30
-rw-r--r--test/passes/jacktest/gcd.fir16
-rw-r--r--test/passes/jacktest/gcd2.fir16
-rw-r--r--test/passes/jacktest/risc.fir50
-rw-r--r--test/passes/jacktest/testlower.fir22
-rw-r--r--test/passes/jacktest/vecshift.fir28
10 files changed, 153 insertions, 153 deletions
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 955d44f2..60b62ac7 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -3,43 +3,43 @@
circuit MemorySearch :
module MemorySearch :
- input target : UInt(4)
- output address : UInt(3)
- input en : UInt(1)
- output done : UInt(1)
+ input target : UInt<4>
+ output address : UInt<3>
+ input en : UInt<1>
+ output done : UInt<1>
- node T_35 = UInt(0, 3)
- reg index : UInt(3)
- index.init := T_35
- node T_36 = UInt(0, 1)
- node T_37 = UInt(4, 3)
- node T_38 = UInt(15, 4)
- node T_39 = UInt(14, 4)
- node T_40 = UInt(2, 2)
- node T_41 = UInt(5, 3)
- node T_42 = UInt(13, 4)
- wire elts : UInt(1)[7]
- elts.0 := Pad(T_36,?)
- elts.1 := Pad(T_37,?)
- elts.2 := Pad(T_38,?)
- elts.3 := Pad(T_39,?)
- elts.4 := Pad(T_40,?)
- elts.5 := Pad(T_41,?)
- elts.6 := Pad(T_42,?)
+ node T_35 = UInt<3>(0)
+ reg index : UInt<3>
+ on-reset index := T_35
+ node T_36 = UInt<1>(0)
+ node T_37 = UInt<3>(4)
+ node T_38 = UInt<4>(15)
+ node T_39 = UInt<4>(14)
+ node T_40 = UInt<2>(2)
+ node T_41 = UInt<3>(5)
+ node T_42 = UInt<4>(13)
+ wire elts : UInt<1>[7]
+ elts[0] := Pad(T_36,?)
+ elts[1] := Pad(T_37,?)
+ elts[2] := Pad(T_38,?)
+ elts[3] := Pad(T_39,?)
+ elts[4] := Pad(T_40,?)
+ elts[5] := Pad(T_41,?)
+ elts[6] := Pad(T_42,?)
accessor elt = elts[index]
node T_43 = bit-not(en)
node T_44 = eq(Pad(elt,?), Pad(target,?))
- node T_45 = UInt(7, 3)
+ node T_45 = UInt<3>(7)
node T_46 = eq(Pad(index,?), Pad(T_45,?))
node T_47 = bit-or(T_44, T_46)
node end = bit-and(T_43, T_47)
when en :
- node T_48 = UInt(0, 1)
+ node T_48 = UInt<1>(0)
index := Pad(T_48,?)
else :
node T_49 = bit-not(end)
when T_49 :
- node T_50 = UInt(1, 1)
+ node T_50 = UInt<1>(1)
node T_51 = add-wrap(Pad(index,?), Pad(T_50,?))
index := Pad(T_51,?)
done := Pad(end,?)
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 733e2036..832bd279 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,35 +3,35 @@
circuit RegisterVecShift :
module RegisterVecShift :
- input load : UInt(1)
- output out : UInt(4)
- input shift : UInt(1)
- input ins : UInt(4)[4]
+ input load : UInt<1>
+ output out : UInt<4>
+ input shift : UInt<1>
+ input ins : UInt<4>[4]
- reg delays : UInt(4)[4]
+ reg delays : UInt<4>[4]
when reset :
- node T_38 = UInt(0, 4)
- node T_39 = UInt(0, 4)
- node T_40 = UInt(0, 4)
- node T_41 = UInt(0, 4)
- wire T_42 : UInt(4)[4]
- T_42.0 := T_38
- T_42.1 := T_39
- T_42.2 := T_40
- T_42.3 := T_41
+ node T_38 = UInt<4>(0)
+ node T_39 = UInt<4>(0)
+ node T_40 = UInt<4>(0)
+ node T_41 = UInt<4>(0)
+ wire T_42 : UInt<4>[4]
+ T_42[0] := T_38
+ T_42[1] := T_39
+ T_42[2] := T_40
+ T_42[3] := T_41
delays := T_42
- node T_43 = UInt(5, 3)
+ node T_43 = UInt<3>(5)
node T_44 = bit-and(Pad(T_43,?), Pad(load,?))
- node T_45 = UInt(4, 3)
+ node T_45 = UInt<3>(4)
node T_46 = eq(Pad(T_44,?), Pad(T_45,?))
when T_46 :
- delays.0 := Pad(ins.0,?)
- delays.1 := Pad(ins.1,?)
- delays.2 := Pad(ins.2,?)
- delays.3 := Pad(ins.3,?)
+ delays[0] := Pad(ins[0],?)
+ delays[1] := Pad(ins[1],?)
+ delays[2] := Pad(ins[2],?)
+ delays[3] := Pad(ins[3],?)
else : when shift :
- delays.0 := Pad(ins.0,?)
- delays.1 := Pad(delays.0,?)
- delays.2 := Pad(delays.1,?)
- delays.3 := Pad(delays.2,?)
- out := Pad(delays.3,?)
+ delays[0] := Pad(ins[0],?)
+ delays[1] := Pad(delays[0],?)
+ delays[2] := Pad(delays[1],?)
+ delays[3] := Pad(delays[2],?)
+ out := Pad(delays[3],?)
diff --git a/test/passes/jacktest/SIntOps.fir b/test/passes/jacktest/SIntOps.fir
index 45ea68f2..406a09de 100644
--- a/test/passes/jacktest/SIntOps.fir
+++ b/test/passes/jacktest/SIntOps.fir
@@ -3,22 +3,22 @@
circuit SIntOps :
module SIntOps :
- input b : SInt(16)
- input a : SInt(16)
- output addout : SInt(16)
- output subout : SInt(16)
- output timesout : SInt(16)
- output divout : SInt(16)
- output modout : SInt(16)
- output lshiftout : SInt(16)
- output rshiftout : SInt(16)
- output lessout : UInt(1)
- output greatout : UInt(1)
- output eqout : UInt(1)
- output noteqout : UInt(1)
- output lesseqout : UInt(1)
- output greateqout : UInt(1)
- output negout : SInt(16)
+ input b : SInt<16>
+ input a : SInt<16>
+ output addout : SInt<16>
+ output subout : SInt<16>
+ output timesout : SInt<16>
+ output divout : SInt<16>
+ output modout : SInt<16>
+ output lshiftout : SInt<16>
+ output rshiftout : SInt<16>
+ output lessout : UInt<1>
+ output greatout : UInt<1>
+ output eqout : UInt<1>
+ output noteqout : UInt<1>
+ output lesseqout : UInt<1>
+ output greateqout : UInt<1>
+ output negout : SInt<16>
node T_35 = add-wrap(a, b)
addout := T_35
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
index 35442ac8..b458ac4a 100644
--- a/test/passes/jacktest/Tlb.fir
+++ b/test/passes/jacktest/Tlb.fir
@@ -2,13 +2,13 @@
; CHECK: Done!
circuit Tbl :
module Tbl :
- output o : UInt(16)
- input i : UInt(16)
- input d : UInt(16)
- input we : UInt(1)
+ output o : UInt<16>
+ input i : UInt<16>
+ input d : UInt<16>
+ input we : UInt<1>
- mem m : UInt(10)[256]
- node T_12 = UInt(0, 1)
+ mem m : UInt<10>[256]
+ node T_12 = UInt<1>(0)
o := Pad(T_12,?)
when we :
accessor T_13 = m[i]
diff --git a/test/passes/jacktest/UIntOps.fir b/test/passes/jacktest/UIntOps.fir
index bb3e6293..e402f22e 100644
--- a/test/passes/jacktest/UIntOps.fir
+++ b/test/passes/jacktest/UIntOps.fir
@@ -3,21 +3,21 @@
circuit UIntOps :
module UIntOps :
- input b : UInt(16)
- input a : UInt(16)
- output addout : UInt(16)
- output subout : UInt(16)
- output timesout : UInt(16)
- output divout : UInt(16)
- output modout : UInt(16)
- output lshiftout : UInt(16)
- output rshiftout : UInt(16)
- output lessout : UInt(1)
- output greatout : UInt(1)
- output eqout : UInt(1)
- output noteqout : UInt(1)
- output lesseqout : UInt(1)
- output greateqout : UInt(1)
+ input b : UInt<16>
+ input a : UInt<16>
+ output addout : UInt<16>
+ output subout : UInt<16>
+ output timesout : UInt<16>
+ output divout : UInt<16>
+ output modout : UInt<16>
+ output lshiftout : UInt<16>
+ output rshiftout : UInt<16>
+ output lessout : UInt<1>
+ output greatout : UInt<1>
+ output eqout : UInt<1>
+ output noteqout : UInt<1>
+ output lesseqout : UInt<1>
+ output greateqout : UInt<1>
node T_31 = add-wrap(a, b)
addout := T_31
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index 2d97ee8d..4be5bdf9 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -3,14 +3,14 @@
;CHECK: To Flo
circuit GCD :
module GCD :
- input b : UInt(16)
- input a : UInt(16)
- input e : UInt(1)
- output z : UInt(16)
- output v : UInt(1)
+ input b : UInt<16>
+ input a : UInt<16>
+ input e : UInt<1>
+ output z : UInt<16>
+ output v : UInt<1>
- reg x : UInt(16)
- reg y : UInt(16)
+ reg x : UInt<16>
+ reg y : UInt<16>
node T_17 = gt(x, y)
when T_17 :
node T_18 = sub-wrap(x, y)
@@ -22,7 +22,7 @@ circuit GCD :
x := a
y := b
z := x
- node T_20 = UInt(0, 1)
+ node T_20 = UInt<1>(0)
node T_21 = eq(y, Pad(T_20,?))
v := T_21
diff --git a/test/passes/jacktest/gcd2.fir b/test/passes/jacktest/gcd2.fir
index e6700122..e0220ca1 100644
--- a/test/passes/jacktest/gcd2.fir
+++ b/test/passes/jacktest/gcd2.fir
@@ -2,14 +2,14 @@
;CHECK: To Flo
circuit GCD :
module GCD :
- input b : UInt(16)
- input a : UInt(16)
- input e : UInt(1)
- output z : UInt(16)
- output v : UInt(1)
+ input b : UInt<16>
+ input a : UInt<16>
+ input e : UInt<1>
+ output z : UInt<16>
+ output v : UInt<1>
- reg x : UInt(16)
- reg y : UInt(16)
+ reg x : UInt<16>
+ reg y : UInt<16>
node T_17 = gt(Pad(x,?), Pad(y,?))
when T_17 :
node T_18 = sub-wrap(Pad(x,?), Pad(y,?))
@@ -21,6 +21,6 @@ circuit GCD :
x := a
y := b
z := x
- node T_20 = UInt(0, 1)
+ node T_20 = UInt<1>(0)
node T_21 = eq(Pad(y,?), Pad(T_20,?))
v := T_21
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 0a13e5c0..bb1512d5 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -3,47 +3,47 @@
circuit Risc :
module Risc :
- output out : UInt(32)
- output valid : UInt(1)
- input boot : UInt(1)
- input isWr : UInt(1)
- input wrAddr : UInt(8)
- input wrData : UInt(32)
+ output out : UInt<32>
+ output valid : UInt<1>
+ input boot : UInt<1>
+ input isWr : UInt<1>
+ input wrAddr : UInt<8>
+ input wrData : UInt<32>
- mem file : UInt(32)[256]
- mem code : UInt(32)[256]
- node T_51 = UInt(0, 8)
- reg pc : UInt(8)
- pc.init := T_51
- node add_op = UInt(0, 1)
- node imm_op = UInt(1, 1)
+ mem file : UInt<32>[256]
+ mem code : UInt<32>[256]
+ node T_51 = UInt<8>(0)
+ reg pc : UInt<8>
+ on-reset pc := T_51
+ node add_op = UInt<1>(0)
+ node imm_op = UInt<1>(1)
accessor inst = code[pc]
node op = bits(inst, 31, 24)
node rci = bits(inst, 23, 16)
node rai = bits(inst, 15, 8)
node rbi = bits(inst, 7, 0)
- node T_52 = UInt(0, 1)
+ node T_52 = UInt<1>(0)
node T_53 = eq(rai, T_52)
- node T_54 = UInt(0, 1)
+ node T_54 = UInt<1>(0)
accessor T_55 = file[rai]
node ra = mux(T_53, T_54, T_55)
- node T_56 = UInt(0, 1)
+ node T_56 = UInt<1>(0)
node T_57 = eq(rbi, T_56)
- node T_58 = UInt(0, 1)
+ node T_58 = UInt<1>(0)
accessor T_59 = file[rbi]
node rb = mux(T_57, T_58, T_59)
- wire rc : UInt(32)
- node T_60 = UInt(0, 1)
+ wire rc : UInt<32>
+ node T_60 = UInt<1>(0)
valid := T_60
- node T_61 = UInt(0, 1)
+ node T_61 = UInt<1>(0)
out := T_61
- node T_62 = UInt(0, 1)
+ node T_62 = UInt<1>(0)
rc := T_62
when isWr :
accessor T_63 = code[wrAddr]
T_63 := wrData
else : when boot :
- node T_64 = UInt(0, 1)
+ node T_64 = UInt<1>(0)
pc := T_64
else :
node T_65 = eq(add_op, op)
@@ -56,15 +56,15 @@ circuit Risc :
node T_69 = bit-or(T_68, rbi)
rc := T_69
out := rc
- node T_70 = UInt(255, 8)
+ node T_70 = UInt<8>(255)
node T_71 = eq(rci, T_70)
when T_71 :
- node T_72 = UInt(1, 1)
+ node T_72 = UInt<1>(1)
valid := T_72
else :
accessor T_73 = file[rci]
T_73 := rc
- node T_74 = UInt(1, 1)
+ node T_74 = UInt<1>(1)
node T_75 = add-wrap(pc, T_74)
pc := T_75
; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/testlower.fir b/test/passes/jacktest/testlower.fir
index c338d094..7b096ff3 100644
--- a/test/passes/jacktest/testlower.fir
+++ b/test/passes/jacktest/testlower.fir
@@ -4,17 +4,17 @@
circuit BundleWire :
module BundleWire :
- input in : { y : UInt(32), x : UInt(32) }
- output outs : { y : UInt(32), x : UInt(32) }[4]
+ input in : { y : UInt<32>, x : UInt<32> }
+ output outs : { y : UInt<32>, x : UInt<32> }[4]
- wire coords : { y : UInt(32), x : UInt(32) }[4]
- coords.0 := in
- outs.0 := coords.0
- coords.1 := in
- outs.1 := coords.1
- coords.2 := in
- outs.2 := coords.2
- coords.3 := in
- outs.3 := coords.3
+ wire coords : { y : UInt<32>, x : UInt<32> }[4]
+ coords[0] := in
+ outs[0] := coords[0]
+ coords[1] := in
+ outs[1] := coords[1]
+ coords[2] := in
+ outs[2] := coords[2]
+ coords[3] := in
+ outs[3] := coords[3]
; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir
index 4d2563af..9914ea04 100644
--- a/test/passes/jacktest/vecshift.fir
+++ b/test/passes/jacktest/vecshift.fir
@@ -4,21 +4,21 @@
circuit VecShiftRegister :
module VecShiftRegister :
- input load : UInt(1)
- output out : UInt(4)
- input shift : UInt(1)
- input ins : UInt(4)[4]
+ input load : UInt<1>
+ output out : UInt<4>
+ input shift : UInt<1>
+ input ins : UInt<4>[4]
- reg delays : UInt(4)[4]
+ reg delays : UInt<4>[4]
when load :
- delays.0 := ins.0
- delays.1 := ins.1
- delays.2 := ins.2
- delays.3 := ins.3
+ delays[0] := ins[0]
+ delays[1] := ins[1]
+ delays[2] := ins[2]
+ delays[3] := ins[3]
else : when shift :
- delays.0 := ins.0
- delays.1 := delays.0
- delays.2 := delays.1
- delays.3 := delays.2
- out := delays.3
+ delays[0] := ins[0]
+ delays[1] := delays[0]
+ delays[2] := delays[1]
+ delays[3] := delays[2]
+ out := delays[3]
; CHECK: Finished Expand Whens
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 17:17:04 +0000