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-rw-r--r--test/passes/jacktest/ALUTop.fir10
-rw-r--r--test/passes/jacktest/Counter.fir5
-rw-r--r--test/passes/jacktest/EnableShiftRegister.fir12
-rw-r--r--test/passes/jacktest/LFSR16.fir11
-rw-r--r--test/passes/jacktest/MemorySearch.fir5
-rw-r--r--test/passes/jacktest/ModuleVec.fir4
-rw-r--r--test/passes/jacktest/RegisterVecShift.fir3
-rw-r--r--test/passes/jacktest/Stack.fir12
-rw-r--r--test/passes/jacktest/VendingMachine.fir3
-rw-r--r--test/passes/jacktest/gcd.fir10
-rw-r--r--test/passes/jacktest/risc.fir7
11 files changed, 48 insertions, 34 deletions
diff --git a/test/passes/jacktest/ALUTop.fir b/test/passes/jacktest/ALUTop.fir
index 74abe0bd..a0aadb11 100644
--- a/test/passes/jacktest/ALUTop.fir
+++ b/test/passes/jacktest/ALUTop.fir
@@ -9,8 +9,8 @@ circuit ALUTop :
input alu_op : UInt<4>
node shamt = bits(B, 4, 0)
- node T_157 = addw(A, B)
- node T_158 = subw(A, B)
+ node T_157 = tail(add(A, B),1)
+ node T_158 = tail(sub(A, B),1)
node T_159 = cvt(A)
node T_160 = dshr(T_159, shamt)
node T_161 = asUInt(T_160)
@@ -50,10 +50,10 @@ circuit ALUTop :
node oot = mux(T_194, T_157, T_193)
node T_195 = bits(oot, 31, 0)
out <= T_195
- node T_196 = bit(alu_op, 0)
- node T_197 = subw(UInt<1>(0), B)
+ node T_196 = bits(alu_op, 0, 0)
+ node T_197 = tail(sub(UInt<1>(0), B),1)
node T_198 = mux(T_196, T_197, B)
- node T_199 = addw(A, T_198)
+ node T_199 = tail(add(A, T_198),1)
sum <= T_199
module ALUdec :
input opcode : UInt<7>
diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index 4e23ba26..266c1849 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -8,9 +8,10 @@ circuit Counter :
output tot : UInt<8>
input amt : UInt<4>
- reg T_13 : UInt<8>,clk,reset,UInt<8>(0)
+ reg T_13 : UInt<8>,clk with :
+ reset => (reset,UInt<8>(0))
when inc :
- node T_14 = addw(T_13, amt)
+ node T_14 = tail(add(T_13, amt),1)
node T_15 = gt(T_14, UInt<8>(255))
node T_16 = mux(T_15, UInt<1>(0), T_14)
T_13 <= T_16
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index d7e91665..9927e83f 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -8,10 +8,14 @@ circuit EnableShiftRegister :
output out : UInt<4>
input shift : UInt<1>
- reg r0 : UInt<4>,clk,reset,UInt<4>(0)
- reg r1 : UInt<4>,clk,reset,UInt<4>(0)
- reg r2 : UInt<4>,clk,reset,UInt<4>(0)
- reg r3 : UInt<4>,clk,reset,UInt<4>(0)
+ reg r0 : UInt<4>,clk with :
+ reset => (reset,UInt<4>(0))
+ reg r1 : UInt<4>,clk with :
+ reset => (reset,UInt<4>(0))
+ reg r2 : UInt<4>,clk with :
+ reset => (reset,UInt<4>(0))
+ reg r3 : UInt<4>,clk with :
+ reset => (reset,UInt<4>(0))
when shift :
r0 <= in
r1 <= r0
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index a4052623..b3fb05cc 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -7,14 +7,15 @@ circuit LFSR16 :
input clk : Clock
input reset : UInt<1>
- reg res : UInt<16>,clk,reset,UInt<16>(1)
+ reg res : UInt<16>,clk with :
+ reset => (reset,UInt<16>(1))
when inc :
- node T_16 = bit(res, 0)
- node T_17 = bit(res, 2)
+ node T_16 = bits(res, 0, 0)
+ node T_17 = bits(res, 2, 2)
node T_18 = xor(T_16, T_17)
- node T_19 = bit(res, 3)
+ node T_19 = bits(res, 3, 3)
node T_20 = xor(T_18, T_19)
- node T_21 = bit(res, 5)
+ node T_21 = bits(res, 5, 5)
node T_22 = xor(T_20, T_21)
node T_23 = bits(res, 15, 1)
node T_24 = cat(T_22, T_23)
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 1abc50a2..39c19dda 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -9,7 +9,8 @@ circuit MemorySearch :
input reset : UInt<1>
output done : UInt<1>
- reg index : UInt<3>,clk,reset,UInt<3>(0)
+ reg index : UInt<3>,clk with :
+ reset => (reset,UInt<3>(0))
wire elts : UInt<4>[7]
elts[0] <= UInt<4>(0)
elts[1] <= UInt<4>(4)
@@ -28,7 +29,7 @@ circuit MemorySearch :
else :
node T_39 = not(end)
when T_39 :
- node T_40 = addw(index, UInt<1>(1))
+ node T_40 = tail(add(index, UInt<1>(1)),1)
index <= T_40
done <= end
address <= index
diff --git a/test/passes/jacktest/ModuleVec.fir b/test/passes/jacktest/ModuleVec.fir
index 9a8e7f2c..6f9b699b 100644
--- a/test/passes/jacktest/ModuleVec.fir
+++ b/test/passes/jacktest/ModuleVec.fir
@@ -5,13 +5,13 @@ circuit ModuleVec :
input in : UInt<32>
output out : UInt<32>
- node T_33 = addw(in, UInt<1>(1))
+ node T_33 = tail(add(in, UInt<1>(1)),1)
out <= T_33
module PlusOne_25 :
input in : UInt<32>
output out : UInt<32>
- node T_34 = addw(in, UInt<1>(1))
+ node T_34 = tail(add(in, UInt<1>(1)),1)
out <= T_34
module ModuleVec :
input ins : UInt<32>[2]
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 61376a62..f138d00a 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -9,7 +9,8 @@ circuit RegisterVecShift :
input shift : UInt<1>
input ins : UInt<4>[4]
- reg delays : UInt<4>[4],clk,reset,delays
+ reg delays : UInt<4>[4],clk with :
+ reset => (reset,delays)
when reset :
wire T_33 : UInt<4>[4]
T_33[0] <= UInt<4>(0)
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index 319e87d5..162bac25 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -11,25 +11,27 @@ circuit Stack :
input dataIn : UInt<32>
cmem stack_mem : UInt<32>[16]
- reg sp : UInt<5>,clk,reset,UInt<5>(0)
- reg out : UInt<32>,clk,reset,UInt<32>(0)
+ reg sp : UInt<5>,clk with :
+ reset => (reset,UInt<5>(0))
+ reg out : UInt<32>,clk with :
+ reset => (reset,UInt<32>(0))
when en :
node T_30 = lt(sp, UInt<5>(16))
node T_31 = and(push, T_30)
when T_31 :
write mport T_32 = stack_mem[sp],clk
T_32 <= dataIn
- node T_33 = addw(sp, UInt<1>(1))
+ node T_33 = tail(add(sp, UInt<1>(1)),1)
sp <= T_33
else :
node T_34 = gt(sp, UInt<1>(0))
node T_35 = and(pop, T_34)
when T_35 :
- node T_36 = subw(sp, UInt<1>(1))
+ node T_36 = tail(sub(sp, UInt<1>(1)),1)
sp <= T_36
node T_37 = gt(sp, UInt<1>(0))
when T_37 :
- node T_38 = subw(sp, UInt<1>(1))
+ node T_38 = tail(sub(sp, UInt<1>(1)),1)
read mport T_39 = stack_mem[T_38],clk
out <= T_39
dataOut <= out
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 79cebbe1..d7822a17 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -8,7 +8,8 @@ circuit VendingMachine :
input clk : Clock
input reset : UInt<1>
- reg state : UInt<3>,clk,reset,UInt<3>(0)
+ reg state : UInt<3>,clk with :
+ reset => (reset,UInt<3>(0))
node T_22 = eq(state, UInt<3>(0))
when T_22 :
when nickel : state <= UInt<3>(1)
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index dd3443f1..31ca30b2 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -10,14 +10,16 @@ circuit GCD :
input a : UInt<16>
input b : UInt<16>
- reg x : UInt<16>,clk,reset,x
- reg y : UInt<16>,clk,reset,y
+ reg x : UInt<16>,clk with :
+ reset => (reset,x)
+ reg y : UInt<16>,clk with :
+ reset => (reset,y)
node T_17 = gt(x, y)
when T_17 :
- node T_18 = subw(x, y)
+ node T_18 = tail(sub(x, y),1)
x <= T_18
else :
- node T_19 = subw(y, x)
+ node T_19 = tail(sub(y, x),1)
y <= T_19
when e :
x <= a
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 46f5a1c2..f722cf97 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -13,7 +13,8 @@ circuit Risc :
cmem file : UInt<32>[256]
cmem code : UInt<32>[256]
- reg pc : UInt<8>,clk,reset,UInt<8>(0)
+ reg pc : UInt<8>,clk with :
+ reset => (reset,UInt<8>(0))
read mport inst = code[pc],clk
node op = bits(inst, 31, 24)
node rci = bits(inst, 23, 16)
@@ -36,7 +37,7 @@ circuit Risc :
else :
node T_56 = eq(UInt<1>(0), op)
when T_56 :
- node T_57 = addw(ra, rb)
+ node T_57 = tail(add(ra, rb),1)
rc <= T_57
node T_58 = eq(UInt<1>(1), op)
when T_58 :
@@ -49,5 +50,5 @@ circuit Risc :
else :
write mport T_62 = file[rci],clk
T_62 <= rc
- node T_63 = addw(pc, UInt<1>(1))
+ node T_63 = tail(add(pc, UInt<1>(1)),1)
pc <= T_63
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 09:47:09 +0000