11 files changed, 22 insertions, 31 deletions

diff --git a/test/passes/jacktest/Counter.fir b/test/passes/jacktest/Counter.fir
index db2b5d62..4e23ba26 100644
--- a/test/passes/jacktest/Counter.fir
+++ b/test/passes/jacktest/Counter.fir
@@ -8,8 +8,7 @@ circuit Counter :
     output tot : UInt<8>
     input amt : UInt<4>
     
-    reg T_13 : UInt<8>,clk,reset
-    onreset T_13 <= UInt<8>(0)
+    reg T_13 : UInt<8>,clk,reset,UInt<8>(0)
     when inc : 
       node T_14 = addw(T_13, amt)
       node T_15 = gt(T_14, UInt<8>(255))
diff --git a/test/passes/jacktest/EnableShiftRegister.fir b/test/passes/jacktest/EnableShiftRegister.fir
index 7937d37f..d7e91665 100644
--- a/test/passes/jacktest/EnableShiftRegister.fir
+++ b/test/passes/jacktest/EnableShiftRegister.fir
@@ -8,14 +8,10 @@ circuit EnableShiftRegister :
     output out : UInt<4>
     input shift : UInt<1>
     
-    reg r0 : UInt<4>,clk,reset
-    onreset r0 <= UInt<4>(0)
-    reg r1 : UInt<4>,clk,reset
-    onreset r1 <= UInt<4>(0)
-    reg r2 : UInt<4>,clk,reset
-    onreset r2 <= UInt<4>(0)
-    reg r3 : UInt<4>,clk,reset
-    onreset r3 <= UInt<4>(0)
+    reg r0 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r1 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r2 : UInt<4>,clk,reset,UInt<4>(0)
+    reg r3 : UInt<4>,clk,reset,UInt<4>(0)
     when shift : 
       r0 <= in
       r1 <= r0
diff --git a/test/passes/jacktest/LFSR16.fir b/test/passes/jacktest/LFSR16.fir
index 770ac3e6..a4052623 100644
--- a/test/passes/jacktest/LFSR16.fir
+++ b/test/passes/jacktest/LFSR16.fir
@@ -7,8 +7,7 @@ circuit LFSR16 :
     input clk : Clock
     input reset : UInt<1>
     
-    reg res : UInt<16>,clk,reset
-    onreset res <= UInt<16>(1)
+    reg res : UInt<16>,clk,reset,UInt<16>(1)
     when inc : 
       node T_16 = bit(res, 0)
       node T_17 = bit(res, 2)
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 1e07596c..1abc50a2 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -9,8 +9,7 @@ circuit MemorySearch :
     input reset : UInt<1>
     output done : UInt<1>
     
-    reg index : UInt<3>,clk,reset
-    onreset index <= UInt<3>(0)
+    reg index : UInt<3>,clk,reset,UInt<3>(0)
     wire elts : UInt<4>[7]
     elts[0] <= UInt<4>(0)
     elts[1] <= UInt<4>(4)
@@ -19,7 +18,7 @@ circuit MemorySearch :
     elts[4] <= UInt<4>(2)
     elts[5] <= UInt<4>(5)
     elts[6] <= UInt<4>(13)
-    infer accessor elt = elts[index]
+    node elt = elts[index]
     node T_35 = not(en)
     node T_36 = eq(elt, target)
     node T_37 = eq(index, UInt<3>(7))
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 8a3223e7..370c84a7 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -25,5 +25,5 @@ circuit Mul :
     tbl[15] <= UInt<4>(9)
     node T_42 = shl(x, 2)
     node T_43 = or(T_42, y)
-    infer accessor T_44 = tbl[T_43]
+    node T_44 = tbl[T_43]
     z <= T_44
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index eb2a0f34..61376a62 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -9,7 +9,7 @@ circuit RegisterVecShift :
     input shift : UInt<1>
     input ins : UInt<4>[4]
     
-    reg delays : UInt<4>[4],clk,reset
+    reg delays : UInt<4>[4],clk,reset,delays
     when reset : 
       wire T_33 : UInt<4>[4]
       T_33[0] <= UInt<4>(0)
diff --git a/test/passes/jacktest/Rom.fir b/test/passes/jacktest/Rom.fir
index 6e4b3cc7..db76b9c7 100644
--- a/test/passes/jacktest/Rom.fir
+++ b/test/passes/jacktest/Rom.fir
@@ -22,5 +22,5 @@ circuit Rom :
     r[13] <= UInt<5>(26)
     r[14] <= UInt<5>(28)
     r[15] <= UInt<5>(30)
-    infer accessor T_39 = r[addr]
+    node T_39 = r[addr]
     out <= T_39
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index ed718331..9b35c3f4 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -1,4 +1,6 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+;CHECK: Finished Low Form Check
+;CHECK-NOT: stack_mem.T_32.mask <= UInt("h0")
 ;CHECK: Done!
 circuit Stack : 
   module Stack : 
@@ -10,16 +12,14 @@ circuit Stack :
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    cmem stack_mem : UInt<32>[16],clk
-    reg sp : UInt<5>,clk,reset
-    onreset sp <= UInt<5>(0)
-    reg out : UInt<32>,clk,reset
-    onreset out <= UInt<32>(0)
+    cmem stack_mem : UInt<32>[16]
+    reg sp : UInt<5>,clk,reset,UInt<5>(0)
+    reg out : UInt<32>,clk,reset,UInt<32>(0)
     when en : 
       node T_30 = lt(sp, UInt<5>(16))
       node T_31 = and(push, T_30)
       when T_31 : 
-        infer accessor T_32 = stack_mem[sp]
+        write mport T_32 = stack_mem[sp],clk
         T_32 <= dataIn
         node T_33 = addw(sp, UInt<1>(1))
         sp <= T_33
@@ -32,6 +32,6 @@ circuit Stack :
       node T_37 = gt(sp, UInt<1>(0))
       when T_37 : 
         node T_38 = subw(sp, UInt<1>(1))
-        infer accessor T_39 = stack_mem[T_38]
+        read mport T_39 = stack_mem[T_38],clk
         out <= T_39
     dataOut <= out
diff --git a/test/passes/jacktest/VendingMachine.fir b/test/passes/jacktest/VendingMachine.fir
index 5ecfe522..79cebbe1 100644
--- a/test/passes/jacktest/VendingMachine.fir
+++ b/test/passes/jacktest/VendingMachine.fir
@@ -8,8 +8,7 @@ circuit VendingMachine :
     input clk : Clock
     input reset : UInt<1>
     
-    reg state : UInt<3>,clk,reset
-    onreset state <= UInt<3>(0)
+    reg state : UInt<3>,clk,reset,UInt<3>(0)
     node T_22 = eq(state, UInt<3>(0))
     when T_22 : 
       when nickel : state <= UInt<3>(1)
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
index 99667b3b..dd3443f1 100644
--- a/test/passes/jacktest/gcd.fir
+++ b/test/passes/jacktest/gcd.fir
@@ -10,8 +10,8 @@ circuit GCD :
     input a : UInt<16>
     input b : UInt<16>
     
-    reg x : UInt<16>,clk,reset
-    reg y : UInt<16>,clk,reset
+    reg x : UInt<16>,clk,reset,x
+    reg y : UInt<16>,clk,reset,y
     node T_17 = gt(x, y)
     when T_17 : 
       node T_18 = subw(x, y)
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index fdc80ee1..e4516db4 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -13,8 +13,7 @@ circuit Risc :
     
     cmem file : UInt<32>[256],clk
     cmem code : UInt<32>[256],clk
-    reg pc : UInt<8>,clk,reset
-    onreset pc <= UInt<8>(0)
+    reg pc : UInt<8>,clk,reset,UInt<8>(0)
     infer accessor inst = code[pc]
     node op = bits(inst, 31, 24)
     node rci = bits(inst, 23, 16)