diff options
Diffstat (limited to 'test/passes/jacktest/risc.fir')
| -rw-r--r-- | test/passes/jacktest/risc.fir | 62 |
1 files changed, 29 insertions, 33 deletions
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index 26a6abdf..875498d6 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -1,6 +1,5 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cTwd | tee %s.out | FileCheck %s -; CHECK: Done! - +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! circuit Risc : module Risc : output out : UInt<32> @@ -13,44 +12,41 @@ circuit Risc : mem file : UInt<32>[256] mem code : UInt<32>[256] reg pc : UInt<8> - on-reset pc := Pad(UInt<8>(0),?) + on-reset pc := UInt<8>(0) accessor inst = code[pc] node op = bits(inst, 31, 24) node rci = bits(inst, 23, 16) node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) - node T_51 = eq(Pad(rai,?), Pad(UInt<1>(0),?)) + node T_51 = eq(rai, UInt<1>(0)) accessor T_52 = file[rai] - node ra = mux(Pad(T_51,?), Pad(UInt<1>(0),?), Pad(T_52,?)) - node T_53 = eq(Pad(rbi,?), Pad(UInt<1>(0),?)) + node ra = mux(T_51, UInt<1>(0), T_52) + node T_53 = eq(rbi, UInt<1>(0)) accessor T_54 = file[rbi] - node rb = mux(Pad(T_53,?), Pad(UInt<1>(0),?), Pad(T_54,?)) + node rb = mux(T_53, UInt<1>(0), T_54) wire rc : UInt<32> - node T_55 = UInt<1>(0) - valid := Pad(T_55,?) - out := Pad(UInt<1>(0),?) - rc := Pad(UInt<1>(0),?) + valid := UInt<1>(0) + out := UInt<1>(0) + rc := UInt<1>(0) when isWr : - accessor T_56 = code[wrAddr] - T_56 := Pad(wrData,?) - else : when boot : pc := Pad(UInt<1>(0),?) + accessor T_55 = code[wrAddr] + T_55 := wrData + else : when boot : pc := UInt<1>(0) else : - node T_57 = eq(Pad(UInt<1>(0),?), Pad(op,?)) - when T_57 : - node T_58 = add-wrap(Pad(ra,?), Pad(rb,?)) - rc := Pad(T_58,?) - node T_59 = eq(Pad(UInt<1>(1),?), Pad(op,?)) - when T_59 : - node T_60 = shl(rai, 8) - node T_61 = bit-or(Pad(T_60,?), Pad(rbi,?)) - rc := Pad(T_61,?) - out := Pad(rc,?) - node T_62 = eq(Pad(rci,?), Pad(UInt<8>(255),?)) - when T_62 : - node T_63 = UInt<1>(1) - valid := Pad(T_63,?) + node T_56 = eq(UInt<1>(0), op) + when T_56 : + node T_57 = add-wrap(ra, rb) + rc := T_57 + node T_58 = eq(UInt<1>(1), op) + when T_58 : + node T_59 = shl(rai, 8) + node T_60 = bit-or(T_59, rbi) + rc := T_60 + out := rc + node T_61 = eq(rci, UInt<8>(255)) + when T_61 : valid := UInt<1>(1) else : - accessor T_64 = file[rci] - T_64 := Pad(rc,?) - node T_65 = add-wrap(Pad(pc,?), Pad(UInt<1>(1),?)) - pc := Pad(T_65,?) + accessor T_62 = file[rci] + T_62 := rc + node T_63 = add-wrap(pc, UInt<1>(1)) + pc := T_63 |