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Diffstat (limited to 'test/passes/jacktest/bundlewire.fir')
| -rw-r--r-- | test/passes/jacktest/bundlewire.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir index cd5b2dfe..cea54ed4 100644 --- a/test/passes/jacktest/bundlewire.fir +++ b/test/passes/jacktest/bundlewire.fir @@ -1,17 +1,17 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -x X -p ct | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit TestLower : module Inst : - input x : UInt - output y : UInt + input data : { w : UInt , x : UInt } + input tag : { y : UInt, z : UInt } module TestLower : mem m : {data : { w : UInt , x : UInt } tag : { y : UInt, z : UInt }}[8] wire index : UInt accessor r = m[index] inst i of Inst - i.x := r + i.data := r.data ; CHECK: Finished Expand Whens |