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Diffstat (limited to 'test/passes/jacktest/bundlewire.fir')
| -rw-r--r-- | test/passes/jacktest/bundlewire.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir index 0d0f0377..0356597e 100644 --- a/test/passes/jacktest/bundlewire.fir +++ b/test/passes/jacktest/bundlewire.fir @@ -1,10 +1,10 @@ -; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s +; RUN: firrtl %s abcefghipj cg | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit BundleWire : module BundleWire : - output in : { y : UInt(32), x : UInt(32) } + input in : { y : UInt(32), x : UInt(32) } output outs : { y : UInt(32), x : UInt(32) }[4] wire coords : { y : UInt(32), x : UInt(32) }[4] |