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Diffstat (limited to 'test/passes/jacktest/Tlb.fir')
| -rw-r--r-- | test/passes/jacktest/Tlb.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir index 35442ac8..b458ac4a 100644 --- a/test/passes/jacktest/Tlb.fir +++ b/test/passes/jacktest/Tlb.fir @@ -2,13 +2,13 @@ ; CHECK: Done! circuit Tbl : module Tbl : - output o : UInt(16) - input i : UInt(16) - input d : UInt(16) - input we : UInt(1) + output o : UInt<16> + input i : UInt<16> + input d : UInt<16> + input we : UInt<1> - mem m : UInt(10)[256] - node T_12 = UInt(0, 1) + mem m : UInt<10>[256] + node T_12 = UInt<1>(0) o := Pad(T_12,?) when we : accessor T_13 = m[i] |