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-rw-r--r--test/passes/jacktest/Tbl.fir3
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index f315aaa9..b916e0f0 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -4,10 +4,11 @@ circuit Tbl :
module Tbl :
input i : UInt<16>
input d : UInt<16>
+ input clk : Clock
output o : UInt<16>
input we : UInt<1>
- cmem m : UInt<10>[256]
+ cmem m : UInt<10>[256],clk
o := UInt<1>(0)
when we :
infer accessor T_13 = m[i]