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Diffstat (limited to 'test/passes/jacktest/RegisterVecShift.fir')
| -rw-r--r-- | test/passes/jacktest/RegisterVecShift.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir index 61376a62..f138d00a 100644 --- a/test/passes/jacktest/RegisterVecShift.fir +++ b/test/passes/jacktest/RegisterVecShift.fir @@ -9,7 +9,8 @@ circuit RegisterVecShift : input shift : UInt<1> input ins : UInt<4>[4] - reg delays : UInt<4>[4],clk,reset,delays + reg delays : UInt<4>[4],clk with : + reset => (reset,delays) when reset : wire T_33 : UInt<4>[4] T_33[0] <= UInt<4>(0) |