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-rw-r--r--test/passes/jacktest/Mul.fir2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/jacktest/Mul.fir b/test/passes/jacktest/Mul.fir
index 14db8769..1552e959 100644
--- a/test/passes/jacktest/Mul.fir
+++ b/test/passes/jacktest/Mul.fir
@@ -24,6 +24,6 @@ circuit Mul :
tbl[14] := UInt<4>(6)
tbl[15] := UInt<4>(9)
node T_42 = shl(x, 2)
- node T_43 = bit-or(T_42, y)
+ node T_43 = or(T_42, y)
infer accessor T_44 = tbl[T_43]
z := T_44