7 files changed, 31 insertions, 31 deletions
diff --git a/test/passes/inline-indexers/bundle-vecs.fir b/test/passes/inline-indexers/bundle-vecs.fir
index 28826056..f4fc609d 100644
--- a/test/passes/inline-indexers/bundle-vecs.fir
+++ b/test/passes/inline-indexers/bundle-vecs.fir
@@ -20,14 +20,14 @@ circuit top :
 
 
       infer accessor b = a[i]
-      ; CHECK: wire b{{[_$]+}}x_1 : UInt<32>
+      ; CHECK: wire b{{[_$]+}}x_2 : UInt<32>
       ; CHECK: node i_1 = i
-      ; CHECK: b{{[_$]+}}x_1 := a{{[_$]+}}0{{[_$]+}}x
-      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_1 := a{{[_$]+}}1{{[_$]+}}x      
-      ; CHECK: wire b{{[_$]+}}y_1 : UInt<32>
+      ; CHECK: b{{[_$]+}}x_2 := a{{[_$]+}}0{{[_$]+}}x
+      ; CHECK: when eqv(i_1, UInt("h1")) : b{{[_$]+}}x_2 := a{{[_$]+}}1{{[_$]+}}x      
+      ; CHECK: wire b{{[_$]+}}y_2 : UInt<32>
       ; CHECK: node i_2 = i
-      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_1
-      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_1
+      ; CHECK: when eqv(i_2, UInt("h0")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y_2
+      ; CHECK: when eqv(i_2, UInt("h1")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y_2
       j := b.x
       b.y := UInt(1)
       
diff --git a/test/passes/inline-indexers/simple.fir b/test/passes/inline-indexers/simple.fir
index ca186e97..095094d3 100644
--- a/test/passes/inline-indexers/simple.fir
+++ b/test/passes/inline-indexers/simple.fir
@@ -12,8 +12,8 @@ circuit top :
       infer accessor a = m[i] 
       o := a
 
-;CHECK: a_1 := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
+;CHECK: a_2 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple2.fir b/test/passes/inline-indexers/simple2.fir
index 3b7d92af..13fc4416 100644
--- a/test/passes/inline-indexers/simple2.fir
+++ b/test/passes/inline-indexers/simple2.fir
@@ -14,12 +14,12 @@ circuit top :
       o1 := a
       o2 := a
 
-;CHECK: wire a_1 : UInt<32>
-;CHECK: a_1 := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
 ;CHECK: wire a_2 : UInt<32>
 ;CHECK: a_2 := m$0
-;CHECK: when eqv(i_2, UInt("h1")) : a_2 := m$1
+;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1
+;CHECK: wire a_3 : UInt<32>
+;CHECK: a_3 := m$0
+;CHECK: when eqv(i_2, UInt("h1")) : a_3 := m$1
 
 
 
diff --git a/test/passes/inline-indexers/simple3.fir b/test/passes/inline-indexers/simple3.fir
index 688958a0..b6a7616c 100644
--- a/test/passes/inline-indexers/simple3.fir
+++ b/test/passes/inline-indexers/simple3.fir
@@ -11,9 +11,9 @@ circuit top :
       infer accessor a = m[i] 
       a := in
 
-;CHECK: wire a_1 : UInt<32>
-;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_1
-;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_1
+;CHECK: wire a_2 : UInt<32>
+;CHECK: when eqv(i_1, UInt("h0")) : m$0 := a_2
+;CHECK: when eqv(i_1, UInt("h1")) : m$1 := a_2
 
 
 
diff --git a/test/passes/inline-indexers/simple4.fir b/test/passes/inline-indexers/simple4.fir
index df045456..129de4de 100644
--- a/test/passes/inline-indexers/simple4.fir
+++ b/test/passes/inline-indexers/simple4.fir
@@ -13,11 +13,11 @@ circuit top :
       infer accessor a = m[i] 
       a.x := in.x
 
-;CHECK: wire a$x_1 : UInt<32>
+;CHECK: wire a$x_2 : UInt<32>
 ;CHECK: node i_1 = i
-;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_1
-;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_1
-;CHECK: a$x_1 := in$x
+;CHECK: when eqv(i_1, UInt("h0")) : m$0$x := a$x_2
+;CHECK: when eqv(i_1, UInt("h1")) : m$1$x := a$x_2
+;CHECK: a$x_2 := in$x
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
 
diff --git a/test/passes/inline-indexers/simple5.fir b/test/passes/inline-indexers/simple5.fir
index 1da83cab..3affa941 100644
--- a/test/passes/inline-indexers/simple5.fir
+++ b/test/passes/inline-indexers/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
          o := a
 
 ;CHECK: when i :
-;CHECK: a_1 := m$0
-;CHECK: when eqv(i_1, UInt("h1")) : a_1 := m$1
+;CHECK: a_2 := m$0
+;CHECK: when eqv(i_1, UInt("h1")) : a_2 := m$1
 ;CHECK: Finished Inline Indexers
 ;CHECK: Done!
diff --git a/test/passes/inline-indexers/simple6.fir b/test/passes/inline-indexers/simple6.fir
index e94efc7a..b177fba2 100644
--- a/test/passes/inline-indexers/simple6.fir
+++ b/test/passes/inline-indexers/simple6.fir
@@ -20,25 +20,25 @@ circuit top :
       write accessor b = a[j] 
       b.x := value
 
-;CHECK: wire b$x_1 : UInt<32>
+;CHECK: wire b$x_2 : UInt<32>
 ;CHECK: node j_1 = j
 ;CHECK: when eqv(j_1, UInt("h0")) :
-;CHECK:    wire a$0$x_1 : UInt<32>
+;CHECK:    wire a$0$x_2 : UInt<32>
 ;CHECK:    node i_1 = i
 ;CHECK:    when eqv(i_1, UInt("h0")) :
-;CHECK:       m$0$0$x := a$0$x_1         
+;CHECK:       m$0$0$x := a$0$x_2         
 ;CHECK:    when eqv(i_1, UInt("h1")) :
-;CHECK:       m$1$0$x := a$0$x_1         
-;CHECK:    a$0$x_1 := b$x_1      
+;CHECK:       m$1$0$x := a$0$x_2         
+;CHECK:    a$0$x_2 := b$x_2      
 ;CHECK: when eqv(j_1, UInt("h1")) :
-;CHECK:    wire a$1$x_1 : UInt<32>
+;CHECK:    wire a$1$x_2 : UInt<32>
 ;CHECK:    node i_2 = i
 ;CHECK:    when eqv(i_2, UInt("h0")) :
-;CHECK:       m$0$1$x := a$1$x_1         
+;CHECK:       m$0$1$x := a$1$x_2         
 ;CHECK:    when eqv(i_2, UInt("h1")) :
-;CHECK:       m$1$1$x := a$1$x_1         
-;CHECK:    a$1$x_1 := b$x_1      
-;CHECK: b$x_1 := value   
+;CHECK:       m$1$1$x := a$1$x_2         
+;CHECK:    a$1$x_2 := b$x_2      
+;CHECK: b$x_2 := value