diff options
Diffstat (limited to 'test/passes/inline-indexers/simple8.fir')
| -rw-r--r-- | test/passes/inline-indexers/simple8.fir | 140 |
1 files changed, 70 insertions, 70 deletions
diff --git a/test/passes/inline-indexers/simple8.fir b/test/passes/inline-indexers/simple8.fir index a02395a7..427dee98 100644 --- a/test/passes/inline-indexers/simple8.fir +++ b/test/passes/inline-indexers/simple8.fir @@ -9,22 +9,22 @@ circuit top : input clock : Clock input reset : UInt<1> - resp[0] := UInt<1>("h00") - resp[1] := UInt<1>("h00") - resp[2] := UInt<1>("h00") - resp[3] := UInt<1>("h00") - write.ready := UInt<1>("h00") - read.ready := UInt<1>("h00") + resp[0] <= UInt<1>("h00") + resp[1] <= UInt<1>("h00") + resp[2] <= UInt<1>("h00") + resp[3] <= UInt<1>("h00") + write.ready <= UInt<1>("h00") + read.ready <= UInt<1>("h00") node waddr = shr(write.bits.addr, 4) node raddr = shr(read.bits.addr, 4) node T_65 = bits(write.bits.way_en, 1, 0) node T_66 = bits(read.bits.way_en, 1, 0) wire T_75 : UInt<128>[2] - T_75[0] := UInt<1>("h00") - T_75[1] := UInt<1>("h00") + T_75[0] <= UInt<1>("h00") + T_75[1] <= UInt<1>("h00") reg T_81 : UInt<12>, clock, reset when read.valid : - T_81 := read.bits.addr + T_81 <= read.bits.addr skip cmem T_84 : UInt<128>[256], clock node T_86 = neq(T_65, UInt<1>("h00")) @@ -37,13 +37,13 @@ circuit top : node T_92 = bit(T_65, 0) node T_93 = bit(T_65, 1) wire T_95 : UInt<1>[2] - T_95[0] := T_92 - T_95[1] := T_93 + T_95[0] <= T_92 + T_95[1] <= T_93 node T_100 = subw(UInt<64>("h00"), T_95[0]) node T_102 = subw(UInt<64>("h00"), T_95[1]) wire T_104 : UInt<64>[2] - T_104[0] := T_100 - T_104[1] := T_102 + T_104[0] <= T_100 + T_104[1] <= T_102 node T_108 = cat(T_104[1], T_104[0]) infer accessor T_109 = T_84[waddr] node T_110 = not(T_108) @@ -51,19 +51,19 @@ circuit top : node T_112 = and(T_91, T_108) node T_113 = or(T_111, T_112) wire T_114 : UInt<128> - T_114 := UInt<1>("h00") - T_114 := T_113 + T_114 <= UInt<1>("h00") + T_114 <= T_113 infer accessor T_116 = T_84[waddr] - T_116 := T_114 + T_116 <= T_114 skip node T_118 = neq(T_66, UInt<1>("h00")) node T_119 = and(T_118, read.valid) reg T_120 : UInt<8>, clock, reset when T_119 : - T_120 := raddr + T_120 <= raddr skip infer accessor T_121 = T_84[T_120] - T_75[0] := T_121 + T_75[0] <= T_121 cmem T_124 : UInt<128>[256], clock node T_126 = neq(T_65, UInt<1>("h00")) node T_127 = and(T_126, write.valid) @@ -75,13 +75,13 @@ circuit top : node T_132 = bit(T_65, 0) node T_133 = bit(T_65, 1) wire T_135 : UInt<1>[2] - T_135[0] := T_132 - T_135[1] := T_133 + T_135[0] <= T_132 + T_135[1] <= T_133 node T_140 = subw(UInt<64>("h00"), T_135[0]) node T_142 = subw(UInt<64>("h00"), T_135[1]) wire T_144 : UInt<64>[2] - T_144[0] := T_140 - T_144[1] := T_142 + T_144[0] <= T_140 + T_144[1] <= T_142 node T_148 = cat(T_144[1], T_144[0]) infer accessor T_149 = T_124[waddr] node T_150 = not(T_148) @@ -89,51 +89,51 @@ circuit top : node T_152 = and(T_131, T_148) node T_153 = or(T_151, T_152) wire T_154 : UInt<128> - T_154 := UInt<1>("h00") - T_154 := T_153 + T_154 <= UInt<1>("h00") + T_154 <= T_153 infer accessor T_156 = T_124[waddr] - T_156 := T_154 + T_156 <= T_154 skip node T_158 = neq(T_66, UInt<1>("h00")) node T_159 = and(T_158, read.valid) reg T_160 : UInt<8>, clock, reset when T_159 : - T_160 := raddr + T_160 <= raddr skip infer accessor T_161 = T_124[T_160] - T_75[1] := T_161 + T_75[1] <= T_161 node T_162 = bits(T_75[0], 63, 0) node T_163 = bits(T_75[1], 63, 0) wire T_165 : UInt<64>[2] - T_165[0] := T_162 - T_165[1] := T_163 + T_165[0] <= T_162 + T_165[1] <= T_163 node T_169 = bits(T_81, 3, 3) infer accessor T_170 = T_165[T_169] wire T_172 : UInt<64>[2] - T_172[0] := T_170 - T_172[1] := T_165[1] + T_172[0] <= T_170 + T_172[1] <= T_165[1] node T_176 = cat(T_172[1], T_172[0]) - resp[0] := T_176 + resp[0] <= T_176 node T_177 = bits(T_75[0], 127, 64) node T_178 = bits(T_75[1], 127, 64) wire T_180 : UInt<64>[2] - T_180[0] := T_177 - T_180[1] := T_178 + T_180[0] <= T_177 + T_180[1] <= T_178 node T_184 = bits(T_81, 3, 3) infer accessor T_185 = T_180[T_184] wire T_187 : UInt<64>[2] - T_187[0] := T_185 - T_187[1] := T_180[1] + T_187[0] <= T_185 + T_187[1] <= T_180[1] node T_191 = cat(T_187[1], T_187[0]) - resp[1] := T_191 + resp[1] <= T_191 node T_192 = bits(write.bits.way_en, 3, 2) node T_193 = bits(read.bits.way_en, 3, 2) wire T_202 : UInt<128>[2] - T_202[0] := UInt<1>("h00") - T_202[1] := UInt<1>("h00") + T_202[0] <= UInt<1>("h00") + T_202[1] <= UInt<1>("h00") reg T_208 : UInt<12>, clock, reset when read.valid : - T_208 := read.bits.addr + T_208 <= read.bits.addr skip cmem T_211 : UInt<128>[256], clock node T_213 = neq(T_192, UInt<1>("h00")) @@ -146,13 +146,13 @@ circuit top : node T_219 = bit(T_192, 0) node T_220 = bit(T_192, 1) wire T_222 : UInt<1>[2] - T_222[0] := T_219 - T_222[1] := T_220 + T_222[0] <= T_219 + T_222[1] <= T_220 node T_227 = subw(UInt<64>("h00"), T_222[0]) node T_229 = subw(UInt<64>("h00"), T_222[1]) wire T_231 : UInt<64>[2] - T_231[0] := T_227 - T_231[1] := T_229 + T_231[0] <= T_227 + T_231[1] <= T_229 node T_235 = cat(T_231[1], T_231[0]) infer accessor T_236 = T_211[waddr] node T_237 = not(T_235) @@ -160,19 +160,19 @@ circuit top : node T_239 = and(T_218, T_235) node T_240 = or(T_238, T_239) wire T_241 : UInt<128> - T_241 := UInt<1>("h00") - T_241 := T_240 + T_241 <= UInt<1>("h00") + T_241 <= T_240 infer accessor T_243 = T_211[waddr] - T_243 := T_241 + T_243 <= T_241 skip node T_245 = neq(T_193, UInt<1>("h00")) node T_246 = and(T_245, read.valid) reg T_247 : UInt<8>, clock, reset when T_246 : - T_247 := raddr + T_247 <= raddr skip infer accessor T_248 = T_211[T_247] - T_202[0] := T_248 + T_202[0] <= T_248 cmem T_251 : UInt<128>[256], clock node T_253 = neq(T_192, UInt<1>("h00")) node T_254 = and(T_253, write.valid) @@ -184,13 +184,13 @@ circuit top : node T_259 = bit(T_192, 0) node T_260 = bit(T_192, 1) wire T_262 : UInt<1>[2] - T_262[0] := T_259 - T_262[1] := T_260 + T_262[0] <= T_259 + T_262[1] <= T_260 node T_267 = subw(UInt<64>("h00"), T_262[0]) node T_269 = subw(UInt<64>("h00"), T_262[1]) wire T_271 : UInt<64>[2] - T_271[0] := T_267 - T_271[1] := T_269 + T_271[0] <= T_267 + T_271[1] <= T_269 node T_275 = cat(T_271[1], T_271[0]) infer accessor T_276 = T_251[waddr] node T_277 = not(T_275) @@ -198,43 +198,43 @@ circuit top : node T_279 = and(T_258, T_275) node T_280 = or(T_278, T_279) wire T_281 : UInt<128> - T_281 := UInt<1>("h00") - T_281 := T_280 + T_281 <= UInt<1>("h00") + T_281 <= T_280 infer accessor T_283 = T_251[waddr] - T_283 := T_281 + T_283 <= T_281 skip node T_285 = neq(T_193, UInt<1>("h00")) node T_286 = and(T_285, read.valid) reg T_287 : UInt<8>, clock, reset when T_286 : - T_287 := raddr + T_287 <= raddr skip infer accessor T_288 = T_251[T_287] - T_202[1] := T_288 + T_202[1] <= T_288 node T_289 = bits(T_202[0], 63, 0) node T_290 = bits(T_202[1], 63, 0) wire T_292 : UInt<64>[2] - T_292[0] := T_289 - T_292[1] := T_290 + T_292[0] <= T_289 + T_292[1] <= T_290 node T_296 = bits(T_208, 3, 3) infer accessor T_297 = T_292[T_296] wire T_299 : UInt<64>[2] - T_299[0] := T_297 - T_299[1] := T_292[1] + T_299[0] <= T_297 + T_299[1] <= T_292[1] node T_303 = cat(T_299[1], T_299[0]) - resp[2] := T_303 + resp[2] <= T_303 node T_304 = bits(T_202[0], 127, 64) node T_305 = bits(T_202[1], 127, 64) wire T_307 : UInt<64>[2] - T_307[0] := T_304 - T_307[1] := T_305 + T_307[0] <= T_304 + T_307[1] <= T_305 node T_311 = bits(T_208, 3, 3) infer accessor T_312 = T_307[T_311] wire T_314 : UInt<64>[2] - T_314[0] := T_312 - T_314[1] := T_307[1] + T_314[0] <= T_312 + T_314[1] <= T_307[1] node T_318 = cat(T_314[1], T_314[0]) - resp[3] := T_318 - read.ready := UInt<1>("h01") - write.ready := UInt<1>("h01") + resp[3] <= T_318 + read.ready <= UInt<1>("h01") + write.ready <= UInt<1>("h01") ;CHECK: Done! |