2 files changed, 47 insertions, 0 deletions
diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir
new file mode 100644
index 00000000..7e9af8df
--- /dev/null
+++ b/test/passes/initialize-regs/bundle-init.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit top :
+   module A :
+      reg r : { x : UInt, flip y : UInt}
+      wire a : UInt
+      wire b : UInt
+      wire w : { x : UInt, flip y : UInt}
+
+      r.x := a
+      r.y := b
+      on-reset r := w
+      
+; CHECK: reg r : { x, flip y}
+; CHECK: r.x := a
+; CHECK: r.y := b
+; CHECK: when reset :
+; CHECK:    r.x := w.x
+; CHECK:    w.y := r.y
+
+
diff --git a/test/passes/initialize-regs/nested-whens.fir b/test/passes/initialize-regs/nested-whens.fir
new file mode 100644
index 00000000..28cbc53d
--- /dev/null
+++ b/test/passes/initialize-regs/nested-whens.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit top :
+   module A :
+      wire p : UInt
+      wire q : UInt
+      reg r : UInt
+      wire a : UInt
+      wire b : UInt
+      wire x : UInt
+      wire y : UInt
+      wire z : UInt
+
+      on-reset r := w
+      when p
+        on-reset r := x
+        r := a
+      when q
+        on-reset r := y
+        r := b
+      r := z
+      
+; CHECK: r := z
+; CHECK: when reset
+; CHECK:    r := q?b:(p?a:w)
+