2 files changed, 7 insertions, 0 deletions
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir
index 6b683e56..08396978 100644
--- a/test/passes/infer-widths/dsh.fir
+++ b/test/passes/infer-widths/dsh.fir
@@ -11,6 +11,9 @@ circuit top :
       wire b : SInt
       wire c : UInt
       wire d : SInt
+      x := UInt(1)
+      y := UInt(1)
+      z := SInt(1)
 
       a := dshl(x,y)
       b := dshl(z,y)
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 590515e7..6a50ae77 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -4,12 +4,16 @@
 circuit top :
    module top :
       wire e : UInt<30>
+      e := UInt(1)
       reg y : UInt
       y := e
 
       wire a : UInt<20>
+      a := UInt(1)
       wire b : UInt<10>
+      b := UInt(1)
       wire c : UInt
+      c := UInt(1)
       wire z : UInt
        
       z := mux(c,a,b)