diff options
Diffstat (limited to 'test/passes/infer-widths')
| -rw-r--r-- | test/passes/infer-widths/dsh.fir | 2 | ||||
| -rw-r--r-- | test/passes/infer-widths/gcd.fir | 4 | ||||
| -rw-r--r-- | test/passes/infer-widths/simple.fir | 2 |
3 files changed, 3 insertions, 5 deletions
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 08396978..47940d25 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd 2>&1 | tee %s.out | FileCheck %s ;CHECK: Infer Widths diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index efed25ad..a83a79a7 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p ctd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p ctd 2>&1 | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : @@ -14,7 +14,6 @@ circuit top : input clk : Clock input reset : UInt<1> output z : UInt<16> - output v : UInt<1> reg x : UInt,clk,reset reg y : UInt,clk,reset onreset x := UInt(0) @@ -32,7 +31,6 @@ circuit top : when e : x := a y := b - v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 1b588c0e..f88afcd6 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -X flo -p cTwd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cTwd 2>&1 | tee %s.out | FileCheck %s ;CHECK: Infer Widths circuit top : |