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-rw-r--r--test/passes/infer-widths/gcd.fir2
-rw-r--r--test/passes/infer-widths/simple.fir10
2 files changed, 10 insertions, 2 deletions
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index a550326b..864852fb 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTd | tee %s.out | FileCheck %s
;CHECK: Infer Widths
circuit top :
diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir
index 432030d5..50eb5452 100644
--- a/test/passes/infer-widths/simple.fir
+++ b/test/passes/infer-widths/simple.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cT | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTwd | tee %s.out | FileCheck %s
;CHECK: Infer Widths
circuit top :
@@ -6,6 +6,14 @@ circuit top :
wire e : UInt(30)
reg y : UInt
y := e
+
+ wire a : UInt(20)
+ wire b : UInt(10)
+ wire c : UInt
+ wire z : UInt
+
+ z := mux(c,Pad(a,?),Pad(b,?))
+
; CHECK: Finished Infer Widths