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-rw-r--r--test/passes/expand-whens/reg-wdoc.fir8
1 files changed, 5 insertions, 3 deletions
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index ad191a01..1de6d8f4 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -1,11 +1,13 @@
; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
circuit top :
module top :
+ input clk : Clock
+ input reset : UInt<1>
wire p : UInt
p := UInt(1)
when p :
- reg r : UInt
- on-reset r := UInt(10)
+ reg r : UInt,clk,reset
+ onreset r := UInt(10)
r := UInt(20)
; CHECK: Expand Whens
@@ -13,7 +15,7 @@ circuit top :
; CHECK: circuit top :
; CHECK: module top :
; CHECK: wire p : UInt
-; CHECK: reg r : UInt
+; CHECK: reg r : UInt, clk, reset
; CHECK: p := UInt(1)
; CHECK: r := mux(reset, UInt(10), UInt(20))