diff options
Diffstat (limited to 'test/passes/expand-whens/reg-wdoc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-wdoc.fir | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index 646397b8..de0bbfd6 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -1,5 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * circuit top : module top : input clk : Clock @@ -17,8 +16,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h00000001") -; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) +; CHECK: p := UInt("h1") +; CHECK-NOT: when p : r := mux(reset, UInt("h1"), UInt("h2")) ; CHECK: Finished Expand Whens |