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Diffstat (limited to 'test/passes/expand-whens/reg-wdc.fir')
-rw-r--r--test/passes/expand-whens/reg-wdc.fir9
1 files changed, 5 insertions, 4 deletions
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index 03f5ade9..bba77902 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -1,4 +1,5 @@
; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; XFAIL: *
circuit top :
module top :
input clk : Clock
@@ -7,16 +8,16 @@ circuit top :
p := UInt(1)
when p :
reg r : UInt,clk,reset
- r := UInt(20)
+ r := UInt(2)
; CHECK: Expand Whens
; CHECK: circuit top :
; CHECK: module top :
; CHECK: wire p : UInt
-; CHECK: reg r : UInt
-; CHECK: p := UInt(1)
-; CHECK: r := UInt(20)
+; CHECK: reg r : UInt, clk, reset
+; CHECK: p := UInt("h00000001")
+; CHECK-NOT: when p : r := UInt("h00000002")
; CHECK: Finished Expand Whens