diff options
Diffstat (limited to 'test/passes/expand-whens/reg-dwc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-dwc.fir | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir deleted file mode 100644 index 6713b1f2..00000000 --- a/test/passes/expand-whens/reg-dwc.fir +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - reg r : UInt,clk with : - reset => (reset,r) - when p : - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p <= UInt<1>("h1") -; CHECK: r <= mux(p, UInt<2>("h2"), r) - -; CHECK: Finished Expand Whens - -; CHECK: Done! - |