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path: root/test/passes/expand-whens/reg-dwc.fir
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Diffstat (limited to 'test/passes/expand-whens/reg-dwc.fir')
-rw-r--r--test/passes/expand-whens/reg-dwc.fir8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index 349c4298..30132723 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -4,10 +4,10 @@ circuit top :
input clk : Clock
input reset : UInt<1>
wire p : UInt
- p := UInt(1)
+ p <= UInt(1)
reg r : UInt,clk,reset
when p :
- r := UInt(2)
+ r <= UInt(2)
; CHECK: Expand Whens
@@ -15,8 +15,8 @@ circuit top :
; CHECK: module top :
; CHECK: wire p : UInt
; CHECK: reg r : UInt
-; CHECK: p := UInt("h1")
-; CHECK: when p : r := UInt("h2")
+; CHECK: p <= UInt("h1")
+; CHECK: when p : r <= UInt("h2")
; CHECK: Finished Expand Whens