diff options
Diffstat (limited to 'test/passes/expand-whens/bundle-init.fir')
| -rw-r--r-- | test/passes/expand-whens/bundle-init.fir | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index f34dbe1a..c4b9f314 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -4,10 +4,10 @@ circuit top : module top : input clk : Clock input reset : UInt<1> - reg r : { x : UInt, y : UInt},clk,reset + wire w : { x : UInt, y : UInt} + reg r : { x : UInt, y : UInt},clk,reset,w wire a : UInt wire b : UInt - wire w : { x : UInt, y : UInt} a <= UInt(1) b <= UInt(2) @@ -15,13 +15,12 @@ circuit top : w.y <= a r.x <= a r.y <= b - onreset r <= w -; CHECK: r$x <= mux(reset, w$x, a) -; CHECK: r$y <= mux(reset, w$y, b) +; CHECK: w.x <= b +; CHECK: w.y <= a +; CHECK: r.x <= a +; CHECK: r.y <= b ; CHECK: a <= UInt("h1") ; CHECK: b <= UInt("h2") -; CHECK: w$x <= b -; CHECK: w$y <= a ; CHECK: Finished Expand Whens |