diff options
Diffstat (limited to 'test/passes/expand-whens/bundle-init.fir')
| -rw-r--r-- | test/passes/expand-whens/bundle-init.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 48336c93..4f8c31e2 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -1,7 +1,7 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s ; CHECK: Expand Whens circuit top : - module A : + module top : reg r : { x : UInt, flip y : UInt} wire a : UInt wire b : UInt @@ -15,11 +15,11 @@ circuit top : r.y := b on-reset r := w -; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1)) +; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1)) ; CHECK: r$y := Register(b, UInt(1)) ; CHECK: a := UInt(1) ; CHECK: b := UInt(2) ; CHECK: w$x := b -; CHECK: w$y := mux-uu(reset, r$y, a) +; CHECK: w$y := mux(reset, r$y, a) ; CHECK: Finished Expand Whens |