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diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
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+; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p cd | tee %s.out | FileCheck %s
+; CHECK: Expand Whens
+circuit top :
+ module A :
+ reg r : { x : UInt, flip y : UInt}
+ wire a : UInt
+ wire b : UInt
+ wire w : { x : UInt, flip y : UInt}
+ a := UInt(1)
+ b := UInt(2)
+
+ w.x := b
+ w.y := a
+ r.x := a
+ r.y := b
+ on-reset r := w
+
+; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1))
+; CHECK: r$y := Register(b, UInt(1))
+; CHECK: a := UInt(1)
+; CHECK: b := UInt(2)
+; CHECK: w$x := b
+; CHECK: w$y := mux-uu(reset, r$y, a)
+
+; CHECK: Finished Expand Whens