aboutsummaryrefslogtreecommitdiff
path: root/test/passes/expand-whens/bundle-init.fir
diff options
context:
space:
mode:
Diffstat (limited to 'test/passes/expand-whens/bundle-init.fir')
-rw-r--r--test/passes/expand-whens/bundle-init.fir6
1 files changed, 4 insertions, 2 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 261ebf02..10da47cf 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -2,7 +2,9 @@
; CHECK: Expand Whens
circuit top :
module top :
- reg r : { x : UInt, flip y : UInt}
+ input clk : Clock
+ input reset : UInt<1>
+ reg r : { x : UInt, flip y : UInt},clk,reset
wire a : UInt
wire b : UInt
wire w : { x : UInt, flip y : UInt}
@@ -13,7 +15,7 @@ circuit top :
w.y := a
r.x := a
r.y := b
- on-reset r := w
+ onreset r := w
; CHECK: when UInt(1) : r$x := mux(reset, w$x, a)
; CHECK: when UInt(1) : r$y := b